參數(shù)資料
型號: MAX354EWE+T
廠商: Maxim Integrated Products
文件頁數(shù): 11/12頁
文件大?。?/td> 0K
描述: IC MULTIPLEXER 8X1 16SOIC
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1,000
功能: 多路復用器
電路: 1 x 8:1
導通狀態(tài)電阻: 350 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 4.5 V ~ 36 V,±4.5 V ~ 18 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 帶卷 (TR)
MAX354/MAX355
Fault-Protected Analog Multiplexers
8
_______________________________________________________________________________________
_________________________________Test Circuits/Timing Diagrams (continued)
+15V
VOUT
-15V
GND
V+
A1
V-
A0
A2
NO8
COM
MAX354
NO1
RS = 50
VIN
EN
10nF
RL
1k
OFF ISOLATION = 20log
VOUT
VIN
10nF
+15V
VOUT
-15V
GND
V+
A1
V-
A0
A2
NO8
COM
MAX354
NO2
RG = 50
VIN
EN
10nF
RL
1k
CROSSTALK = 20log
VOUT
VIN
10nF
NO1
R = 1k
+15V
-15V
GND
V+
A2
V-
A1
A0
NO8
MAX354
CHANNEL
SELECT
NO1
COM
EN
1MHz
CAPACITANCE
ANALYZER
f = 1MHz
Figure 5. Off Isolation
Figure 6. Crosstalk
Figure 7. NO/COM Capacitance
_______________Detailed Description
Fault-Protection Circuitry
Maxim’s MAX354/MAX355 are fully fault protected for
continuous input voltages up to ±40V, whether or not
the V+ and V- power supplies are present. These
devices use a “series FET” protection scheme that not
only protects the multiplexer output from overvoltage,
but also limits the input current to sub-microamp levels.
When signal voltages exceed or are within approxi-
mately 1.5V of the supply rails, on-resistance increas-
es. This greater on-resistance limits fault currents and
output voltage, protecting sensitive circuits and com-
ponents. The protected output clamps at approximately
1.5V below the supply rails and maintains the correct
polarity. There are no glitches or polarity reversals
going into or coming out of a fault condition.
Figures 8 and 9 show how the series FET circuit protects
against overvoltage conditions. When power is off, the
gates of all three FETs are at ground. With a -25V input,
N-channel FET Q1 is turned on by the +25V gate-to-
source voltage. The P-channel device (Q2), however,
has +25V VGS and is turned off, thereby preventing the
input signal from reaching the output. If the input volt-
age is +25V, Q1 has a negative VGS, which turns it off.
Similarly, only sub-microamp leakage currents can flow
from the output back to the input, since any voltage will
turn off either Q1 or Q2.
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