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參數(shù)資料
型號： MAX350EWN+T
廠商： Maxim Integrated Products
文件頁數(shù)： 2/20頁
文件大?。?/td> 0K
描述： IC MULTIPLEXER DUAL 4X1 18SOIC
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 1,000
功能： 多路復用器
電路： 2 x 4:1
導通狀態(tài)電阻： 100 歐姆
電壓電源： 單/雙電源
電壓 - 電源，單路/雙路(±)： 2.7 V ~ 16 V，±2.7 V ~ 8 V
電流 - 電源： 1µA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 18-SOIC（0.295"，7.50mm 寬）
供應商設備封裝： 18-SOIC W
包裝： 帶卷 (TR)
Note 1: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
Note 2:
RON = RON(max) - RON(min). On-resistance match between channels and on-resistance flatness are guaranteed only with
specified voltages. Flatness is defined as the difference between the maximum and minimum value of on-resistance as
measured over the specified analog signal range.
Note 3: Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at room temp.
Note 4: Guaranteed by design.
Note 5: Leakage testing at single supply is guaranteed by testing with dual supplies.
Note 6: See Figure 6. Off-isolation = 20log10 VCOM/VNO, VCOM = output. NO = input to off switch.
Note 7: Between any two switches. See Figure 3.
MAX349/MAX350
Serially Controlled, Low-Voltage,
8-Channel/Dual 4-Channel Multiplexers
10
______________________________________________________________________________________
TIMING CHARACTERISTICS—Single +3V Supply (Figure 1)
(V+ = +3.0V to +3.6V, V- = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
SERIAL DIGITAL INTERFACE
RESET Minimum Pulse Width
(Note 4)
tRW
105
ns
TA = +25°C
Allowable Fall Time at DIN, SCLK
(Note 4)
tSCF
2
s
20% of V+ to 70% of V+,
CL = 10pF
C, E, M
Fall Time of DOUT (Note 4)
tDF
100
ns
20% of V+ to 70% of V+,
CL = 10pF
C, E, M
Rise Time of DOUT (Note 4)
tDR
100
ns
20% of V+ to 70% of V+,
CL = 10pF
C, E, M
Allowable Rise Time at DIN,
SCLK (Note 4)
tSCR
2
s
20% of V+ to 70% of V+,
CL = 10pF
C, E, M
DIN Data Valid after Falling SCLK
(Note 4)
tDO
400
ns
Data Hold Time (Note 4)
Minimum Data Setup Time
(Note 4)
tDS
38
120
ns
tDH
-38
150
50% of SCLK to 10% of
DOUT, CL = 10pF
SCLK Low Time (Note 4)
ns
tCL
C, E, M
190
ns
TA = +25°C
C, E, M
PARAMETER
SYMBOL
MIN
TYP
MAX
(Note 1)
UNITS
C, E, M
SCLK High Time (Note 4)
CS Lag Time (Note 4)
tCSH2
240
ns
tCH
190
CS Lead Time (Note 4)
Cycle Time (Note 4)
SCLK Frequency
fSCLK
ns
0
2.1
MHz
tCH +tCL
480
tCSS
240
ns
C, E, M
ns
C, E, M
CONDITIONS
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