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參數(shù)資料
| 型號： | MAX349 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Serially Controlled, Low-Voltage, 8-Channel Multiplexers(接通電阻100Ω,漏電流0.1nA,導通速率0.275μs,串行控制多路轉換器) |
| 中文描述： | 串行控制、低電壓、8通道和雙4通道多路復用器 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 214K |
| 代理商： | MAX349 |
M
S erially Controlled, Low-Voltage,
8-Channel/Dual 4-Channel Multiplexers
______________________________________________________________________________________
17
Power-S upply Considerations
Overview
The MAX349/MAX350 construction is typical of most
CMOS analog switches. It has three supply pins: V+, V-
and GND. V+ and V- are used to drive the internal
CMOS switches, and they set the limits of the analog
voltage on any switch. Reverse ESD-protection diodes
are internally connected between each analog signal
pin and both V+ and V-. If any analog signal exceeds
V+ or V-, one of these diodes will conduct. During normal
operation, these (and other) reverse-biased ESD diodes
leak, forming the only current drawn from V+ or V-.
Virtually all the analog leakage current is through the
ESD diodes. Although the ESD diodes on a given sig-
nal pin are identical, and therefore fairly well balanced,
they are reverse biased differently. Each is biased by
either V+ or V- and the analog signal. This means their
leakages vary as the signal varies. The difference in the
two diode leakages to the V+ and V- pins constitutes
the analog signal-path leakage current. All analog leak-
age current flows to the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of either the same or
opposite polarity.
There is no connection between the analog signal
paths and GND.
V+ and GND power the internal logic and logic-level
translators, and set both the input and output logic lim-
its. The logic-level translators convert the logic levels to
switched V+ and V- signals to drive the analog signal
gates. This drive signal is the only connection between
the logic supplies (and signals) and the analog sup-
plies. V+ and V- have ESD-protection diodes to GND.
The logic-level inputs and output have ESD protection
to V+ and to GND.
The logic-level thresholds are CMOS and TTL compati-
ble when V+ is +5V. As V+ rises, the threshold increases
slightly. Therefore, when V+ reaches +12V, the threshold
is about 3.1V; above the TTL-guaranteed high-level mini-
mum of 2.8V, but still compatible with CMOS outputs.
FOUR CLOCK
PULSES
DIN
SCLK
D4
SW4
D
0
SW
0
Figure 7. Differential Multiplexer Input Control
CS
SCLK
DIN
MAX349
MAX350
CS
SCLK
DIN
MAX349
MAX350
CS
SCLK
DIN
MAX349
MAX350
TOOTHER
SERIAL
DEVICES
DIN
SCLK
CS1
CS2
CS3
Figure 6. Addressable Serial Interface
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