參數(shù)資料
型號(hào): MAX3353EEUE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): 穩(wěn)壓器
英文描述: USB On-the-Go Charge Pump with Switchable Pullup/Pulldown Resistors
中文描述: 0.015 A SWITCHED CAPACITOR REGULATOR, 600 kHz SWITCHING FREQ-MAX, PDSO16
封裝: 4.40 MM, MO-153AB, TSSOP-16
文件頁(yè)數(shù): 5/21頁(yè)
文件大?。?/td> 386K
代理商: MAX3353EEUE
M
USB On-the-Go Charge Pump with Switchable
Pullup/Pulldown Resistors
_______________________________________________________________________________________
5
TIMING CHARACTERISTICS (continued)
(V
CC
= +2.6V to +5.5V, V
L
= +1.65V to V
CC
, V
TRM
= +3V to +3.6V, C
FLYING
= 0.1μF, V
CC
decoupled with 1μF capacitor to ground.
V
TRM
and V
L
decoupled with 0.1μF capacitor to ground. C
VBUS
= 1μF (min), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical val-
ues are at T
A
= +25
°
C, V
CC
= +4V, V
L
= +1.8V, V
TRM
= +3.3V.) (Notes 3, 4)
PARAMETER
SYMBOL
CONDITION
INT
Out Fall Time
C
LOAD
= 50pF
ID_OUT Rise Time
C
LOAD
= 50pF
ID_OUT Fall Time
C
LOAD
= 50pF
Time to Exit Shutdown
Time to Enter Shutdown
MIN
TYP
20
30
10
500
1000
MAX
UNITS
ns
ns
ns
μs
μs
I
2
C/SMBUS-COMPATIBLE TIMING SPECIFICATIONS
(V
CC
= +2.6V to +5.5V, V
L
= +1.65V to V
CC
, V
TRM
= +3V to +3.6V, C
FLYING
= 0.1μF, V
CC
decoupled with 1μF capacitor to ground.
V
TRM
and V
L
decoupled with 0.1μF capacitor to ground. C
VBUS
= 1μF (min). T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical val-
ues are at V
CC
= +4V, V
L
= +1.8V, V
TRM
= +3.3V, and T
A
= +25
°
C.) (Notes 3, 4)
PARAMETER
SYMBOL
f
SCL
CONDITION
MIN
DC
TYP
MAX
400
UNITS
kHz
Serial Clock Frequency
Bus Free Time Between Stop and
Start Conditions
t
BUF
1.3
μs
Start Condition Hold Time
Stop Condition Setup Time
Clock Low Period
Clock High Period
Data Setup Time
Data Hold Time
t
HD:STA
t
SU:STO
t
LOW
t
HIGH
t
SU:DAT
t
HD:DAT
0.6
0.6
1.3
0.6
100
0
μs
μs
μs
μs
ns
μs
(Note 7)
0.9
Maximum Receive SCL/SDA Rise
Time
t
R
(Note 8)
300
ns
Minimum Receive SCL/SDA Rise
Time
t
R
(Note 8)
20 + 0.1C
B
ns
Maximum Receive SCL/SDA Fall
Time
t
F
(Note 8)
300
ns
Minimum Receive SCL/SDA Fall
Time
t
F
(Note 8)
20 + 0.1C
B
ns
t
F
t
F
t
SP
C
B
= 400pF, I
SDA
= 3mA, V
L
2.5V
C
B
= 50pF, I
SDA
= 3mA, V
L
< 2.5
(Note 9)
20 + 0.1C
B
20 + 0.1C
B
250
250
Transmit SDA Fall Time (Note 4)
ns
Pulse Width of Suppressed Spike
50
ns
Note 3:
All currents into the device are negative; currents out of the device are positive. All voltages are referenced to device
ground unless otherwise specified.
Note 4:
Parameters are 100% production tested at +25
°
C, limits over temperature are guaranteed by design.
Note 5:
The V
BUS
current source and current gate time vary together with process and temperature such that the resulting V
BUS
pulse is guaranteed to drive a <13μF load to a voltage >2.0V, and to drive a >96μF load to a volatge <2.2V. See the
SRP
V
BUS
Pulsing
section for an explanation of this self-timed pulse.
Note 6:
Guaranteed by design, not production tested.
Note 7:
A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL
s falling
edge.
Note 8:
C
B
is total capacitance of one bus line in pF. Tested with C
B
= 400pF.
Note 9:
Input filters on SDA, SCL, and ADD suppress noise spikes less than 50ns.
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