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參數(shù)資料
| 型號： | MAX3272AETP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP LIMITING 20-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 限幅放大器 |
| 應(yīng)用： | 光纖學(xué)網(wǎng)絡(luò) |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-TQFN-EP（4x4） |
| 包裝： | 帶卷 (TR) |
MAX3272/MAX3272A
+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
_______________________________________________________________________________________
5
Pin Description
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
15.0
15.5
16.0
16.5
17.0
17.5
18.0
18.5
19.0
100k
1M
10M
100M
COMMON-MODE REJECTION RATIO
vs. FREQUENCY
MAX3272
toc13
FREQUENCY (Hz)
COMMON-MODE
REJECTION
RATIO
(dB)
PIN
NAME
FUNCTION
1, 4, 17
GND
Supply Ground
2
IN+
Noninverted Input Signal
3
IN-
Inverted Input Signal
5TH
Loss-of-Signal Threshold Pin. Resistor to ground sets the LOS threshold.
6, 12, 15, 20
VCC
Power Supply
7
CLOS
LOS Time-Constant Capacitor Connection. For SONET applications, CCLOS = 0.01F is recommended.
8
SQUELCH
Squelch Input. The squelch function is disabled when SQUELCH is not connected or set to TTL low
level. When SQUELCH is set to TTL high level and LOS is asserted, the data outputs (OUT+, OUT-)
are forced to static levels.
9
LOS
Noninverted Loss-of-Signal Output. LOS is asserted TTL high when the signal drops below the assert
threshold set by the TH input. The MAX3272 does not have ESD protection on this pin. The
MAX3272A has ESD protection on this pin.
10
LOS
Inverted Loss-of-Signal Output. LOS is asserted TTL low when the signal drops below the assert
threshold set by the TH input. The MAX3272 does not have ESD protection on this pin. The
MAX3272A has ESD protection on this pin.
11
LEVEL
Output Current Level. When this pin is not connected, the CML output current is approximately
16mA. When this pin is connected to ground, the output current increases to about 20mA.
13
OUT-
Inverted Data Output
14
OUT+
Noninverted Data Output
16
OUTPOL
Output Polarity Control Input. Connect to GND for an inversion of polarity through the limiting
amplifier and connect to VCC for normal operation.
18
CAZ2
Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and CAZ1
extends the time constant of the offset correction loop. Typical value of CAZ is 0.1F.
19
CAZ1
Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and CAZ2
extends the time constant of the offset correction loop. Typical value of CAZ is 0.1F.
EP
EXPOSED
PAD
Connect the exposed paddle to board ground for optimal electrical and thermal performance.
0
4
2
8
6
10
12
0
2500
LOS ASSERT AND DEASSERT LEVELS
vs. DATA RATE
MAX3272
toc14
DATA RATE (Mbps)
V
IN
(mV
P-P
)
1000
500
1500
2000
223 - 1 PRBS PATTERN
RTH = 20k
CIN = 0.1
F
DEASSERT
ASSERT
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