參數(shù)資料
型號(hào)： MAX3172
廠商： Maxim Integrated Products, Inc.
英文描述： Quad LVDS Receiver 16-TSSOP -40 to 85
中文描述： +3.3V、多協(xié)議、軟件可選的電纜端接器及收發(fā)器
文件頁數(shù)： 14/19頁
文件大?。?/td> 276K
代理商： MAX3172
M
+3.3V Multiprotocol Software-Selectable
Cable Terminators and Transceivers
14
______________________________________________________________________________________
In Figure 11, the MAX3170 and MAX3172/MAX3174 are
placed in V.28 mode. Switches S1 and S2 are opened
on the MAX3172/MAX3174 to place the network in high-
Z mode. Switch S3 is closed on the MAX3170 to enable
the 5k
terminating resistor.
V.28 Interface
The V.28 interface is an unbalanced single-ended inter-
face (Figure 12). The V.28 driver generates a minimum
of ±5V across the load impedance between A' and C'.
The V.28 receiver specification calls for input trip points
at ±3V. To aid in rejecting system noise, the MAX3170
V.28 receiver has a typical hysteresis of 0.5V. Also, the
MAX3172/MAX3174 have more tightly specified input
trip points to guarantee fail-safe operation (see
Fail-
Safe
).
The MAX3172/MAX3174 V.28 receiver provides an
internal 5k
termination resistance.
V.10 Interface
The V.10 interface (Figure 12) is an unbalanced single-
ended interface capable of driving a 450
load. The
V.10 driver generates a minimum voltage of ±4V
(V
ODO
) across A' and C' when unloaded and a mini-
mum voltage of ±0.9
V
ODO
when loaded with 450
.
The V.10 receiver input trip threshold is defined
between +300mV and -300mV with input impedance
characteristics shown in Figure 13.
The MAX3172/MAX3174 V.10 mode receiver has a
threshold between +25mV and +250mV to ensure that
the receiver has proper fail-safe operation (see
Fail-
Safe
). To aid in rejecting system noise, the MAX3172/
MAX3174 V.10 receiver has a typical hysteresis of
15mV. Switch S3 in Figure 14 is open in V.10 mode to
disable the 5k
V.28 termination at the receiver input.
Receiver Glitch Rejection
To allow operation in an unterminated or otherwise
noisy system, the MAX3172 features 10μs of receiver
input glitch rejection. The glitch-rejection circuitry
blocks the reception of high-frequency noise with a bit
period less than 5μs while receiving low-frequency sig-
nals with a bit period greater than 15μs, allowing glitch-
free operation in unterminated systems at up to 64kbps.
Figure 12. Typical V.28 and V.10 Interface
A
′
C
′
A
C
GENERATOR
UNBALANCED
INTERCONNECTING
CABLE
CABLE
TERMINATION
RECEIVER
LOAD
Figure 11. V.28 Termination and Internal Resistance Networks
R6
10k
R8
5k
R3
127
R2
52
R1
52
A
′
B
′
C
′
A
B
GND
R5
30k
R7
10k
R4
30k
MAX3172
MAX3174
MAX3170
S3
S2
S1
RECEIVER
Figure 13. V.10 Receiver Input Impedance
-3.25mA
3.25mA
-10V
+10V
-3V
+3V
V
Z
I
Z
相關(guān)PDF資料
PDF描述
MAX3172CAI Quad LVDS Receiver 16-TSSOP -40 to 85
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