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參數(shù)資料
| 型號(hào)： | MAX3111E |
| 廠商： | Maxim Integrated Products, Inc. |
| 元件分類： | RS-232 |
| 英文描述： | 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors |
| 中文描述： | 5V的高速RS - 232收發(fā)器與0.1uF電容 |
| 文件頁(yè)數(shù)： | 21/32頁(yè) |
| 文件大?。?/td> | 413K |
| 代理商： | MAX3111E |
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M
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
______________________________________________________________________________________
21
UART Software Shutdown
When in software shutdown, the UART’s oscillator turns
off to reduce power dissipation. The UART enters shut-
down by a software command (SHDNi bit = 1). The
software shutdown is entered upon completing the
transmission of the data in both the Transmit register
and the Transmit-Buffer register. The SHDNo bit is set
when the UART enters shutdown. The microcontroller
(μC) monitors the SHDNo bit to determine when the
UART is shut down and then shuts down the
RS-232 transceivers.
Software shutdown clears the receive FIFO, R, RA/FE,
D0r–D7r, Pr, and Pt registers and sets the T bit high.
Configuration bits (
RM
,
TM
,
PM
,
RAM
, IR, ST, PE, L,
B0–B3, and RTS) are programmable when SHDNo = 1
and CTS is also readable. Although RA is reset upon
entering shutdown, it goes high when any transitions
are detected on the RX pin. This allows the UART to
monitor activity on the receiver when in shutdown.
When taking the part out of software shutdown (SHDNi
= 0), the oscillator turns on when
CS
goes high. After
CS
goes high, the oscillator typically takes about 25ms
to stabilize. Configure the UART after the oscillator has
stabilized by using a write configuration that clears all
registers but RTS and CTS. If a framing error occurs,
you may have not waited long enough for the oscillator
to stabilize.
The hardware shutdown affects only the RS-232 trans-
ceiver, and the software shutdown affects only the
UART. See the RS-232 Transceiver Hardware
Shutdown section.
Dual Charge-Pump Voltage Converter
The internal power supply consists of a regulated dual
charge pump that provides output voltages of +5.5V
(doubling charge pump) and -5.5V (inverting charge
pump), using a +3.3V supply (MAX3111E) or a +5V sup-
ply (MAX3110E). The charge pump operates in discontin-
uous mode; if the output voltages are less than 5.5V, the
charge pump is enabled, and if the output voltages
exceed 5.5V, the charge pump is disabled. Each charge
pump includes internal flying capacitors and reservoir
capacitors to generate the V+ and V- supplies.
Table 7. Interrupt Sources and Masks—Bit Descriptions
MEANING
WHEN SET
DESCRIPTION
Received parity bit = 1
Transition on RX when
in shutdown; framing
error when not in
shutdown
RA/FE
RAM
This is the RA (RX-transition) bit in shutdown, and the framing-error (FE) bit in
operating mode. RA is set if there has been a transition on RX since entering
shutdown. RA is cleared when the MAX3110E/MAX3111E exits shutdown.
IRQ
is
asserted when RA is set and
RAM
= 1.
FE is determined solely by the currently received data and is not stored in FIFO.
The FE bit is set if a zero is received when the first stop bit is expected. FE is
cleared upon receipt of the next properly framed character.
IRQ
is asserted
when FE is set and
RAM
= 1.
MASK
BIT
Pr
PM
The Pr bit reflects the value in the word currently in the receive-buffer register
(oldest data available). The Pr bit is set when parity is enabled (PE = 1) and the
received parity bit is 1. The Pr bit is cleared either when parity is not enabled (PE
= 0) or when parity is enabled and the received bit is 0. An interrupt is issued
based on the oldest Pr value in the receiver FIFO. The oldest Pr value is the next
value read by a Read Data operation.
BIT
NAME
Data available
R
RM
The R bit is set when new data is available to be read or when data is being read
from the receive register/FIFO. FIFO is cleared when all data has been read. An
interrupt is asserted as long as R = 1 and
RM
= 1.
Transmit buffer is
empty
T
TM
The T bit is set when the transmit buffer is ready to accept data.
IRQ
is asserted
low if
TM
= 1 and the transmit buffer becomes empty. This source is cleared on
the rising edge of SCLK’s 16th clock pulse when using a Read Data or Write
Data operation.
CS
’s rising edge during a Read Data operation. Although the
interrupt is cleared, poll T to determine transmit-buffer status.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3111ECNI | 功能描述:UART 接口集成電路 RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| MAX3111ECNI+G36 | 功能描述:UART 接口集成電路 5V SPI/uWire Compatible RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| MAX3111ECW1+G36 | 制造商:IC'S/TRANSISTORS/DIO 功能描述: 制造商:IC'S/TRANSISTORS/DIODES 功能描述: |
| MAX3111ECWI | 功能描述:UART 接口集成電路 RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| MAX3111ECWI+ | 制造商:Maxim Integrated Products 功能描述:LINE TRNSCVR 2TR 2TX 2RX 28SOIC W - Rail/Tube |
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