參數(shù)資料
型號： MAX3110ECNI+G36
廠商： Maxim Integrated Products
文件頁數(shù)： 13/31頁
文件大小： 0K
描述： IC TXRX RS232 SPI W/CAP 28-DIP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 14
特點： 收發(fā)器
通道數(shù)： 1，UART
規(guī)程： RS232，RS485
電源電壓： 4.5 V ~ 5.5 V
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶CMOS： 是
安裝類型： 通孔
封裝/外殼： 28-DIP（0.300"，7.62mm）
供應商設備封裝： 28-PDIP
包裝： 管件
產(chǎn)品目錄頁面： 1404 (CN2011-ZH PDF)
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Baud-Rate Generator
The baud-rate generator determines the rate at which
the transmitter and receiver operate. Bits B3–B0 in the
write configuration register determine the baud-rate
divisor (BRD), which divides the X1 oscillator frequen-
cy. The on-board oscillator operates with either a
1.8432MHz or a 3.6864MHz crystal or is driven at X1
with a 45% to 55% duty-cycle square wave. Table 6
shows baud-rate divisors for given input codes as well
as the baud rate for 1.8432MHz and 3.684MHz crystals.
The generator’s clock is 16-times the baud rate.
Interrupt Sources and Masks
Using the Read Data or Write Data register clears the
interrupt IRQ, assuming the conditions that initiated the
interrupt no longer exist. Table 7 gives the details for
each interrupt source. Figure 6 shows the functional
diagram for the interrupt sources and mask blocks.
Following are two examples of setting up an IRQ for the
MAX3110E/MAX3111E:
Example 1. Set up only the transmit buffer-empty inter-
rupt. Send the 16-bit word below into DIN of the
MAX3110E/MAX3111E using the Write Configuration
register. This 16-bit word configures the MAX3110E/
MAX3111E for 9600bps, 8-bit words, no parity, and one
stop bit with a 1.8432MHz crystal.
binary 1100100000001010
HEX C80A
Example 2. Set up only the data-available (or data-
being-read) interrupt.
Send the 16-bit word below into DIN of the
MAX3110E/MAX3111E using the Write Configuration
register. This 16-bit word configures the MAX3110E/
MAX3111E for 9600bps, 8-bit words, no parity, and one
stop bit with a 1.8432MHz crystal.
binary 1100010000001010
HEX C40A
Receive FIFO
The MAX3110E/MAX3111E contain an 8-word receive
FIFO for data received by the UART to minimize
processor overhead. Using the UART-software shut-
down clears the receive FIFO. Upon power-up, the
receive FIFO is enabled. To disable the receive FIFO,
set the FEN bit high when writing to the Write
Configuration register. To check whether the FIFO is
enabled or disabled, read back the FEN bit using the
Read Configuration.
Table 6. Baud-Rate Selection*
115.2k
230.4k**
BAUD
RATE
(fOSC =
3.6864MHz)
BAUD
B3
B2 B1 B0
2
00
0
1
0
0**
DIVISION
RATIO
57.6k
115.2k**
BAUD
RATE
(fOSC =
1.8432MHz)
28.8k
57.6k
8
00
1
4
00
1
0
14.4k
28.8k
7200
14.4k
1800
3600
128
01
1
64
01
1
0
900
1800
32
01
0
1
16
01
0
3600
7200
38.4k
76.8k
9600
19.2k
24
10
1
12
10
1
0
4800
9600
2400
4800
600
1200
384
11
1
192
11
1
0
300
600
96
11
0
1
48
11
0
1200
2400
6
10
0
1
3
10
0
19.2k
38.4k
IRQ
N
RM MASK
TM MASK
PM MASK
TRANSITION ON RX
SHUTDOWN
RAM MASK
FRAMING ERROR
SHUTDOWN
RAM MASK
R
S
Q
NEW DATA AVAILABLE
DATA READ
TRANSMIT BUFFER EMPTY
DATA READ
PE = 1 AND RECEIVED
PARITY BIT = 1
PE = 0 OR RECEIVED
PARITY BIT = 0
R
S
Q
R
S
Q
Figure 6. Functional Diagram for Interrupt Sources and Mask
Blocks
*Standard baud rates shown in bold
**Default baud rate
20
Maxim Integrated
MAX3110E/MAX3111E
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