參數(shù)資料
型號(hào): MAX3000A
廠商: Altera Corporation
英文描述: Programmable Logic Device Family
中文描述: 可編程邏輯器件系列
文件頁(yè)數(shù): 32/42頁(yè)
文件大小: 649K
代理商: MAX3000A
32
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 21. EPM3512A External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-7
-10
Min
Max
Min
Max
t
PD1
t
PD2
Input to non-registered output
I/O input to non-registered
output
Global clock setup time
Global clock hold time
Global clock setup time of fast
input
Global clock hold time of fast
input
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for clear
and preset
Minimum global clock period
Maximum internal global clock
frequency
Minimum array clock period
Maximum internal array clock
frequency
C1 = 35 pF
(2)
C1 = 35 pF
(2)
7.5
7.5
10.0
10.0
ns
ns
t
SU
t
H
t
FSU
(2)
(2)
5.6
0.0
3.0
7.6
0.0
3.0
ns
ns
ns
t
FH
0.0
0.0
ns
t
CO1
t
CH
t
CL
t
ASU
t
AH
t
ACO1
t
ACH
t
ACL
t
CPPW
C1 = 35 pF
1.0
3.0
3.0
2.5
0.2
1.0
3.0
3.0
3.0
4.7
1.0
4.0
4.0
3.5
0.3
1.0
4.0
4.0
4.0
6.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
(2)
C1 = 35 pF
(2)
7.8
10.4
(3)
t
CNT
f
CNT
(2)
(2)
,
(4)
8.6
11.5
ns
MHz
116.3
87.0
t
ACNT
f
ACNT
(2)
(2)
,
(4)
8.6
11.5
ns
MHz
116.3
87.0
Table 22. EPM3512A Internal Timing Parameters (Part 1 of 3)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-7
-10
Min
Max
Min
Max
t
IN
t
IO
t
FIN
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.7
0.7
3.1
0.9
0.9
3.6
ns
ns
ns
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