參數(shù)資料
型號: MAX2442EAI
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 無繩電話/電話
英文描述: 900MHz Image-Reject Receivers
中文描述: TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PDSO28
封裝: 5.30 MM, 6.50 MM PITCH, SSOP-28
文件頁數(shù): 7/12頁
文件大?。?/td> 107K
代理商: MAX2442EAI
M
900MHz Image-Rejec t Rec eivers
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7
Pin Desc ription
DIV1
18
Driving DIV1 with a logic high disables the divide-by-64/65 prescaler and connects the PREOUT pin
directly to an oscillator buffer amplifier, which outputs -8dBm into a 50
load. Tie DIV1 low for divide-by-
64/65 operation. Pull this pin low when in shutdown to minimize off current.
RXON
VCOON
MOD
16
Driving RXON with a logic high enables the LNA, receive mixer, and IF output buffer. VCOON must also
be high.
17
Driving VCOON with a logic high turns on the VCO, phase shifters, VCO buffers, and prescaler. The
prescaler can be selectively disabled by floating the PREGND pin.
19
Modulus Control for the Divide-by-64/65 Prescaler: high = divide-by-64, low = divide-by-65. Note that
the DIV1 pin must be at logic low when using the prescaler mode.
PREGND
PREOUT
20
V
CC
11
Supply Voltage Input for Signal-Path Blocks, except LNA. Bypass with a 47pF low-inductance capacitor
and 0.01μF to GND (pin 8 recommended).
GND
8
Ground Connection for Signal-Path Blocks, except LNA. Connect directly to ground plane.
NAME
V
CC
CAP1
RXOUT
GND
7
Ground Connection for Receive Low-Noise Amplifier. Connect directly to ground plane using multiple vias.
LNAGAIN
10
Low-Noise Amplifier Gain-Control Input. Drive this pin high for maximum gain. When LNAGAIN is pulled
low, the LNA is capacitively bypassed and the supply current is reduced by 4.5mA. This pin can also be
driven with an analog voltage to adjust the LNA gain in intermediate states. Refer to the Receiver Gain
vs. LNAGAIN Voltage graph in the Typical Operating Characteristics, as well as Table 1.
PIN
FUNCTION
1
Supply-Voltage Input for Master Bias Cell. Bypass with a 47pF low-inductance capacitor and 0.1μF to
GND (pin 28 recommended).
2
Receive Bias Compensation Pin. Bypass with a 47pF low-inductance capacitor and 0.01μF to GND.
Do not make any other connections to this pin.
Single-Ended, 330
IF Output. AC couple to this pin.
3
Ground connection for the Prescaler. Tie PREGND to ground for normal operation. Leave floating to
disable the prescaler and the output buffer. Tie MOD and DIV1 to ground and leave PREOUT floating
when disabling the prescaler.
21
Prescaler/Oscillator Buffer Output. In divide-by-64/65 mode (DIV1 = low), the output level is 500mVp-p
into a high-impedance load. In divide-by-1 mode (DIV1 = high), this output delivers -8dBm into a 50
load. AC couple to this pin.
GND
RXIN
V
CC
4, 9,
12–15
Ground Connection
5
Receiver RF Input, single-ended. The input match shown in Figure 1 maintains an input VSWR of better
than 2:1 from 902MHz to 928MHz.
6
Supply Voltage Input for Receive Low-Noise Amplifier. Bypass with a 47pF low-inductance capacitor to
GND (pin 7 recommended).
V
CC
22
Supply-Voltage Input for Prescaler. Bypass with a 47pF low-inductance capacitor and 0.01μF to GND
(pin 20 recommended).
V
CC
23
Supply-Voltage Input for VCO and Phase Shifters. Bypass with a 47pF low-inductance capacitor to GND
(pin 26 recommended).
TANK
24
Differential Oscillator Tank Port. See Applications Informationfor information on tank circuits or on using
an external oscillator.
TANK
25
Differential Oscillator Tank Port. See Applications Informationfor information on tank circuits or on using
an external oscillator.
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