參數(shù)資料
型號: MAX2106UCM
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 衰減器
英文描述: DBS Direct Downconverter
中文描述: RF/MICROWAVE DOWN CONVERTER
封裝: 7 X 7 MM, 1 MM HEIGHT, MS-026ABA-HD, TQFP-48
文件頁數(shù): 7/10頁
文件大?。?/td> 182K
代理商: MAX2106UCM
M
DBS Direct Downconverter
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7
Pin Description (continued)
NAME
FUNCTION
PIN
34
MOD-
PECL Modulus Control. A PECL low on MOD- sets the dual-modulus prescaler to divide by 32. A
PECL logic high sets the divide ratio to 33. Drive with a differential PECL signal in conjunction with
MOD+ (pin 33).
PECL Phase-Locked Loop Input. Drive with a differential PECL signal in conjunction with PLLIN- (pin 36).
PECL Phase-Locked Loop Input. Drive with a differential PECL signal in conjunction with PLLIN+ (pin 35)
35
36
PLLIN+
PLLIN-
37
LOBUF+/
PSOUT+
LOBUFSEL = GND: PECL Prescaler Output. Differential output of the dual-modulus prescaler. Used in
conjunction with PSOUT-. Requires PECL-compatible termination. LOBUFSEL=V
CC
: 50
LO buffer
noninverting output.
42
43
44
47
48
TANK-
VRLO
TANK+
FB
CP
LO Tank Oscillator Input. Connect to an external LC tank with varactor tuning.
LO Internal Regulator. Bypass with a 1000pF ceramic chip capacitor to GND.
LO Tank Oscillator Input. Connect to an external LC tank with varactor tuning.
Feedback Input for Loop Filter
Voltage Drive Output. Control of external charge-pump transistor.
38
LOBUF-/
PSOUT-
LOBUFSEL = GND: PECL Prescaler Output. Differential output of the dual-modulus prescaler. Used in
conjunction with PSOUT+. Requires PECL-compatible termination.
LOBUFSEL = V
CC
: 50
LO buffer inverting output.
50%
MOD+,
MOD-
PSOUT+
PSOUT-
50%
50%
50%
t
SUM
t
HM
Figure 1. Modulus Control Timing Diagram
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