參數(shù)資料
型號(hào)： MAX2078CTK+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 12/26頁(yè)
文件大?。?/td> 0K
描述： IC FRNT-END ULTRASOUND 8CH 68QFN
應(yīng)用說(shuō)明： Ultrasound Imaging Systems Application Note
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： 超聲波接收器
應(yīng)用： 醫(yī)療用超聲波成像，聲納
安裝類(lèi)型： 表面貼裝
封裝/外殼： 68-TQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 68-TQFN-EP（10x10）
包裝： 帶卷 (TR)
MAX2078
Octal-Channel Ultrasound Front-End
with CW Doppler Mixers
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(
Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0°C to +70°C, VGND = 0V,
CLP = 0, PD = 0, no RF signals applied. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25°C, unless otherwise noted.) (Note 5)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC_ to GND .........................................................-0.3V to +5.5V
VCC2 - VCC1......................................................................> -0.3V
CI_, CQ_ to GND ....................................................-0.3V to +13V
ZF_, IN_, AG to GND ................................-0.3V to (VCC_ + 0.3V)
INC_ ..............................................................................20mA DC
VREF to GND.............................................................-0.3V to +3V
IN_ to AG ...............................................................-0.6V to +0.6V
OUT_, LO_, DIN, DOUT, VG_, NP,
CS, CLK, PD,
CLP, V/C to GND......................................-0.3V to VCC1 + 0.3V
CI_, CQ_, VCC_, VREF analog and digital control signals must
be applied in this order
Input Differential Voltage .............................2.0VP-P differential
Continuous Power Dissipation (TA = +70°C)
68-Pin TQFN (derated 40mW/°C above +70°C) ..................4W
Operating Temperature Range (Note 1).................0°C to +70°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-40°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3.3V Supply Voltage
VCC1
3.13
3.3
3.47
V
4.75V/5V Supply Voltage
VCC2
4.5
4.75
5.25
V
External Reference Voltage RangeVREF
(Note 6)
2.475
2.525
V
CMOS Input High Voltage
VIH
Applies to CMOS control inputs
2.5
V
CMOS Input Low Voltage
VIL
Applies to CMOS control inputs
0.8
V
CMOS Input Leakage Current
IIN
TA = +25
oC, applies to CMOS control inputs;
0 to 3.47V
10
A
DATA Output High Voltage
DOUT_HI
10M
Ω load
VCC1
V
DATA Output Low Voltage
DOUT_LO
10M
Ω load
0
V
DC ELECTRICAL CHARACTERISTICS—VGA MODE
(
Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0°C to +70°C, VGND = 0V,
NP = 0, V/C = 1, CLP = 0, PD = 0, no RF signals applied. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25°C, unless other-
wise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4.75V/5V Supply Standby Current
I_NP_5V_TOT NP = 1, all channels
3.9
6
mA
3V Supply Standby Current
I_NP_3V_TOT NP = 1, all channels
1.7
3
mA
4.75V/5V Power-Down Current
I_PD_5V_TOT PD = 1, all channels
0.4
10
A
Note 2: Junction temperature TJ = TC + (
θJC x VCC x ICC). This formula can only be used if the component is soldered down to a printed
circuit board pad containing multiple ground vias to remove the heat. The junction temperature must not exceed 150°C.
Note 3: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Note 4: Junction temperature TJ = TA + (
θJA x VCC x ICC), assuming there is no heat removal from the exposed pad. The junction
temperature must not exceed 150°C.
64 TQFN
Junction-to-Ambient Thermal Resistance (
θJA)........20°C/W
Junction-to-Case Thermal Resistance (
θJC)............0.5°C/W
PACKAGE THERMAL CHRACTERISTICS (Notes 2, 3, 4)
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