參數(shù)資料
型號(hào)： MAX2038CCQ+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 9/24頁(yè)
文件大?。?/td> 0K
描述： IC VGA W/OCTAL MIXER 8CH 100TQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 90
類型： 可變?cè)鲆娣糯笃?br>
應(yīng)用： 醫(yī)療用超聲波成像，聲納
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤(pán)
MAX2038
Ultrasound VGA Integrated
with CW Octal Mixer
______________________________________________________________________________________
17
Mode 2
The LO_LVDS input frequency is 8 x fLO (typ) for mode
2 operation. The CWD LO frequency range is 1MHz to
7.5MHz, and the input frequency ranges from 8MHz to
60MHz. This high LO clock frequency requires a differ-
ential LVDS input. The 8 x fLO input is then divided by 8
to produce 8 phases. These 8 phases are generated
for each of the 8 channels and programmed for the
selected phase by the serial shift register. Note that the
serial shift register is common to modes 1, 2, 3, and
where each channel has a corresponding 5-bit shift
register, which is used to program the output phase.
However, since mode 2 generates 8 phases only, 3 of
the 4 phase-programming bits are used; 5 bits are still
loaded per channel using the serial shift register, but
the phase-programming MSB is a don’t-care bit. The
fifth bit in the shift register always turns each channel
on/off individually. For mode 2, set CW_M1 to a logic-
low and set CW_M2 to a logic-high. See Table 3.
Mode 3
The LO_LVDS input is not used in this mode. Separate
4 x fLO clock inputs are provided using LO1–LO8 for
each channel. The CWD LO frequency range is 1MHz
to 7.5MHz, and the input frequency provides ranges
from 4MHz to 30MHz. Note that the LO clock frequency
can utilize 3V CMOS inputs. The 4 x fLO LO1–LO8
inputs are divided by 4 to produce 4 phases. These
4 phases are generated for each of the 8 channels and
programmed for the selected phase by the serial shift
register. For mode 3, 4 phases are generated, and only
2 of the 4 phase-programming bits are required where
the 2-phase programming MSBs are “don’t-care” bits.
For mode 3, set CW_M1 to a logic-high and set CW_M2
to a logic-low. See Table 4.
Mode 4
The LO_LVDS input is not used in this mode. The
appropriate phases are externally provided using sepa-
rate 4 x fLO LO1–LO8 inputs for each channel. A 4 x fLO
input is required so the device can internally generate
accurate duty-cycle independent quadrature LO drives.
Note that the serial shift register is not used in this
mode. The CWD LO frequency range is 1MHz to
7.5MHz and the input frequency ranges from 4MHz to
30MHz. The appropriate inputs are provided at LO1 to
LO8. A reset line is provided to the customer so that
they can synchronize all the CWD channels. The reset
line is implemented through the RESET. For mode 4, set
both CW_M1 and CW_M2 to logic-high. See Table 5.
MODE 2
CW_M1 = 0
CW_M2 = 1
MSB
LSB
SHUTDOWN
DCBA
SD
PHASE
(DEG)
(B0)
(B1)
(B2)
(B3)
(B4)
0
DC
000
0/1
45
DC
0
1
0/1
90
DC
0
1
0
0/1
135
DC
0
1
0/1
180
DC
1
0
0/1
225
DC
1
0
1
0/1
270
DC
1
0
0/1
315
DC
1
0/1
Table 3. Mode 2 Logic Table (DC = Don’t
Care, B4 = 0: Channel On/B4 = 1: Channel
Off)
MODE 3
CW_M1 = 1
CW_M2 = 0
MSB
LSB
SHUTDOWN
DC
BA
SD
PHASE
(DEG)
(B0)
(B1)
(B2)
(B3)
(B4)
0
DC
0
0/1
90
DC
0
1
0/1
180
DC
1
0
0/1
270
DC
1
0/1
Table 4. Mode 3 Logic Table (DC = Don’t
Care, B4 = 0: Channel On/B4 = 1: Channel
Off)
MODE 4
CW_M1 = 1
CW_M2 = 1
MSB
LSB
SHUTDOWN
DCBA
SD
PHASE
(DEG)
(B0)
(B1)
(B2)
(B3)
(B4)
Serial bus
not used in
mode 4
N/A
Table 5. Mode 4 Logic Table
N/A = Not applicable.
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