參數(shù)資料
型號(hào): MAX198BCAI+
廠商: Maxim Integrated Products
文件頁數(shù): 14/16頁
文件大小: 0K
描述: IC DAS 12BIT 6CH 28-SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 46
類型: 數(shù)據(jù)采集系統(tǒng)(DAS)
分辨率(位): 12 b
采樣率(每秒): 100k
數(shù)據(jù)接口: 并聯(lián)
電壓電源: 單電源
電源電壓: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 管件
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
_______________________________________________________________________________________
7
______________________________________________________________Pin Description
Digital Ground
DGND
28
+5V Supply. Bypass with 0.1F capacitor to AGND.
VDD
27
In the internal acquisition mode, when CS is low, a rising edge on WR latches in configuration data and starts an
acquisition plus a conversion cycle. In the external acquisition mode, when CSis low, the first rising edge on WR
starts an acquisition, and a second rising edge on WR ends acquisition and starts a conversion cycle.
WR
26
PIN
Chip Select, active low
CS
2
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock. In internal clock mode,
place a capacitor (CCLK) from this pin to ground to set the internal clock frequency; fCLK = 1.56MHz typical
with CCLK = 100pF.
CLK
1
FUNCTION
NAME
100k
510k
24k
REFADJ
+5V
0.01
F
MAX196
MAX198
Figure 1. Reference-Adjust Circuit
3k
DOUT
+5V
a) High-Z to VOH and VOL to VOH
b) High-Z to VOL and VOH to VOL
CLOAD
Figure 2. Load Circuits for Enable Time
_______________Detailed Description
Converter Operation
The MAX196/MAX198 multirange, fault-tolerant ADCs
use successive approximation and internal input
track/hold (T/H) circuitry to convert an analog signal to
a 12-bit digital output. The 12-bit parallel-output format
provides easy interface to microprocessors (Ps).
Figure 3 shows the MAX196/MAX198 in the simplest
operational configuration.
Analog-Input Track/Hold
In the internal acquisition control mode (control bit D5
set to 0), the T/H enters its tracking mode on WR’s ris-
ing edge, and enters its hold mode when the internally
timed (6 clock cycles) acquisition interval ends. In bipo-
lar mode and unipolar mode (MAX196 only), a low-
impedance input source, which settles in less than
1.5s, is required to maintain conversion accuracy at
the maximum conversion rate.
When the MAX198 is configured for unipolar mode, the
input does not need to be driven from a low-impedance
source. The acquisition time (tAZ) is a function of the
source output resistance (RS), the channel input resis-
tance (RIN), and the T/H capacitance.
Three-State Digital I/O, D11 = MSB
D11–D0
3–14
Analog Ground
AGND
15
Analog Input Channels
CH0–CH5
16–21
Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01F capacitor to AGND. Connect
to VDD when using an external reference at the REF pin.
REFADJ
22
Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a
4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal
buffer by pulling REFADJ to VDD.
REF
23
INT goes low when conversion is complete and output data is ready.
INT
24
If CS is low, a falling edge on RD will enable a read operation on the data bus.
RD
25
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