參數(shù)資料
型號(hào): MAX197BEWI+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 2/16頁(yè)
文件大?。?/td> 0K
描述: IC DAS 12BIT SNGL 28-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 25
類型: 數(shù)據(jù)采集系統(tǒng)(DAS)
分辨率(位): 12 b
采樣率(每秒): 100k
數(shù)據(jù)接口: 并聯(lián)
電壓電源: 單電源
電源電壓: 4.75 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1393 (CN2011-ZH PDF)
MAX197
How to Start a Conversion
Conversions are initiated with a write operation, which
selects the mux channel and configures the MAX197 for
either unipolar or bipolar input range. A write pulse (WR
+ CS) can either start an acquisition interval or initiate a
combined acquisition plus conversion. The sampling
interval occurs at the end of the acquisition interval.
The ACQMOD bit in the input control byte offers two
options for acquiring the signal: internal or external.
The conversion period lasts for 12 clock cycles in either
internal or external clock or acquisition mode.
Writing a new control byte during conversion cycle will
abort conversion and start a new acquisition interval.
Internal Acquisition
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this six-clock-cycle acquisition interval (3s with
fCLK = 2MHz) ends. See Figure 5.
External Acquisition
Use the external acquisition timing mode for precise con-
trol of the sampling aperture and/or independent control
of acquisition and conversion times. The user controls
acquisition and start-of-conversion with two separate
write pulses. The first pulse, written with ACQMOD = 1,
starts an acquisition interval of indeterminate length. The
second write pulse, written with ACQMOD = 0, termi-
nates acquisition and starts conversion on WR’s rising
edge (Figure 6). However, if the second control byte
contains ACQMOD = 1, an indefinite acquisition interval
is restarted.
The address bits for the input mux must have the same
values on the first and second write pulses. Power-
down mode bits (PD0, PD1) can assume new values on
the second write pulse (see Power-Down Mode).
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
10
______________________________________________________________________________________
tCS
tCSWS
tWR
tACQI
tCONV
tDH
tDS
tINT1
tD0
tD01
tTR
HGH-Z
tCSRS
tCSRH
CS
WR
D7–D0
INT
RD
HBEN
DOUT
ACQMOD ="0"
HIGH / LOW
BYTE VALID
HIGH / LOW
BYTE VALID
CONTROL
BYTE
tCSWH
Figure 5. Conversion Timing Using Internal Acquisition Mode
Table 6. Data-Bus Output
PIN
HBEN = LOW
HBEN = HIGH
D0
B0 (LSB)
B8
D1
B1
B9
D2
B2
B10
D3
B3
B11 (MSB)
D4
B4
B11 (BIP = 1) / 0 (BIP = 0)
D5
B5
B11 (BIP = 1) / 0 (BIP = 0)
D6
B6
B11 (BIP = 1) / 0 (BIP = 0)
D7
B7
B11 (BIP = 1) / 0 (BIP = 0)
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