參數資料
型號: MAX197
廠商: Maxim Integrated Products, Inc.
英文描述: Multi-Range Single +5V, 12-Bit DAS with 8+4 Bus Interface(8通道,100ksps,并行,12位A/D轉換器)
中文描述: 多量程(±10V, ±5V, +10V, +5V)、單+5V、12位數DAS,8+4總線接口
文件頁數: 7/16頁
文件大?。?/td> 165K
代理商: MAX197
M
Multi-Range (±10V, ±5V, +10V, +5V ),
S ingle +5V, 12-Bit DAS with 8+4 Bus Interfac e
_______________________________________________________________________________________
7
______________________________________________________________Pin Desc ription
Digital Ground
DGND
28
+5V Supply. Bypass with 0.1μF capacitor to AGND.
V
DD
27
INT goes low when conversion is complete and output data is ready.
INT
24
Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01μF capacitor to AGND. Connect
to V
DD
when using an external reference at the REF pin.
REFADJ
25
Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a
4.096V nominal output, externally adjustable at REFADJ . In external reference mode, disable the internal
buffer by pulling REFADJ to V
DD
.
REF
26
Three-State Digital I/O. D2 output (HBEN = low), D10 output (HBEN = high).
Three-State Digital I/O. D1 output (HBEN = low), D9 output (HBEN = high).
Three-State Digital I/O. D0 output (HBEN = low), D8 output (HBEN = high). D0 = LSB.
Analog Ground
Analog Input Channels
D2/D10
D1/D9
D0/D8
AGND
CH0–CH7
12
13
14
15
16–23
Used to multiplex the 12-bit conversion result. When high, the 4 MSBs are multiplexed on the data bus;
when low, the 8 LSBs are available on the bus.
HBEN
5
Shutdown. Puts the device into full power-down (FULLPD) mode when pulled low.
Three-State Digital I/O
Three-State Digital I/O. D3 output (HBEN = low), D11 output (HBEN = high).
SHDN
D7–D4
D3/D11
6
7–10
11
If CS is low, a falling edge on RD will enable a read operation on the data bus.
RD
4
When CS is low, in the internal acquisition mode, a rising edge on WRlatches in configuration data and starts an
acquisition plus a conversion cycle. When CS is low, in the external acquisition mode, the first rising edge on
WR starts an acquisition and a second rising edge on WR ends acquisition and starts a conversion cycle.
WR
3
PIN
Chip Select, active low.
CS
2
Clock Input. In external clock mode, drive CLK with a TTL/CMOS compatible clock. In internal clock mode,
place a capacitor from this pin to ground to set the internal clock frequency; f
CLK
= 1.56MHz typical with
C
CLK
= 100pF.
CLK
1
FUNCTION
NAME
100k
510k
24k
REFADJ
+5V
0.01
μ
F
MAX197
Figure 1. Reference-Adjust Circuit
3k
3k
D
OUT
D
OUT
+5V
a. High-Z to V
OH
and V
OL
to V
OH
b. High-Z to V
OL
and V
OH
to V
OL
C
LOAD
C
LOAD
Figure 2. Load Circuits for Enable Time
相關PDF資料
PDF描述
MAX197BCWI ECONOLINE: RJ & RG - Dual Output from a Single Input Rail - 3kVDC & 4kVDC Isolation - Optional Continuous Short Circuit Protected - Custom Solutions Available - UL94V-0 Package Material - Efficiency to 84%
MAX197AENI Multi-Range (【10V, 【5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface
MAX197AEWI Multi-Range (【10V, 【5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface
MAX197BCNI Multi-Range (【10V, 【5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface
MAX197BENI Multi-Range (【10V, 【5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface
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