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參數(shù)資料
| 型號： | MAX194BCWE+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 85KSPS SHTDN 16SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 46 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 85k |
| 數(shù)據(jù)接口： | QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 80mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個單端，雙極 |
| 產(chǎn)品目錄頁面： | 1393 (CN2011-ZH PDF) |
Input Acquisition and Settling
Four conversion-clock periods are allocated for acquir-
ing the input signal. At the highest conversion rate, four
clock periods is 2.4s. If more than three clock cycles
have occurred since the end of the previous conver-
sion, conversion begins on the next falling clock edge
after CONV goes low. Otherwise, bringing CONV low
begins a conversion on the fourth falling clock edge
after the previous conversion. This scheme ensures the
minimum input acquisition time is four clock periods.
Most applications require an input buffer amplifier. If
the input signal is multiplexed, the input channel should
be switched near the beginning of a conversion, rather
than near the end of or after a conversion (Figure 13).
This allows time for the input buffer amplifier to respond
to a large step change in input signal. The input amplifi-
er must have a high enough slew rate to complete the
required output voltage change
before the beginning of
the acquisition time.
At the beginning of acquisition, the capacitive DAC is
connected to the amplifier output, causing some output
disturbance. Ensure that the sampled voltage has set-
tled to within the required limits before the end of the
acquisition time. If the frequency of interest is low, AIN
can be bypassed with a large enough capacitor to
charge the capacitive DAC with very little change in
voltage (Figure 14). However, for AC use, AIN must be
driven by a wideband buffer (at least 10MHz), which
must be stable with the DAC’s capacitive load (in paral-
lel with any AIN bypass capacitor used) and also must
settle quickly (Figure 15 or 16).
Digital Noise
Digital noise can easily be coupled to AIN and REF.
The conversion clock (CLK) and other digital signals
that are active during input acquisition contribute noise
to the conversion result. If the noise signal is synchro-
nous to the sampling interval, an effective input offset is
produced. Asynchronous signals produce random
noise on the input, whose high-frequency components
may be aliased into the frequency band of interest.
Minimize noise by presenting a low impedance (at the
frequencies contained in the noise signal) at the inputs.
This requires bypassing AIN to AGND, or buffering the
input with an amplifier that has a small-signal band-
width of several megahertz, or preferably both. AIN has
a bandwidth of about 16MHz.
Offsets resulting from synchronous noise (such as the
conversion clock) are canceled by the MAX194’s cali-
bration scheme. However, because the magnitude of
the offset produced by a synchronous signal depends
on the signal’s shape, recalibration may be appropriate
if the shape or relative timing of the clock or other digi-
tal signals change, as might occur if more than one
clock signal or frequency is used.
Distortion
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the MAX194’s
THD (-90dB, or 0.0032%) at frequencies of interest. If
the chosen amplifier has insufficient common-mode
rejection, which results in degraded THD performance,
use the inverting configuration (positive input ground-
ed) to eliminate errors from this source. Low tempera-
ture-coefficient, gain-setting resistors reduce linearity
errors caused by resistance changes due to self-heat-
ing. Also, to reduce linearity errors due to finite amplifier
gain, use an amplifier circuit with sufficient loop gain at
the frequencies of interest (Figures 14, 15, 16).
MAX194
14-Bit, 85ksps ADC with 10A Shutdown
______________________________________________________________________________________
15
MAX410
4
7
6
2
3
IN
+5V
-5V
0.1
F
0.01
F
22
510
0.1
F
AIN
Figure 16. ±5V Buffer for AC/DC Use Has ±3.5V Swing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX194BCWE+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14Bit 85ksps 5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX194BCWE+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14Bit 85ksps 5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX194BCWE-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX194BEPE | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX194BEPE+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14Bit 85ksps 5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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