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參數(shù)資料
| 型號： | MAX192 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Low-Power, 8-Channel,Serial 10-Bit ADC(8通道,133ksps串行10位A/D轉(zhuǎn)換器) |
| 中文描述： | 低功耗、8通道、串行10位ADC |
| 文件頁數(shù)： | 6/24頁 |
| 文件大小： | 211K |
| 代理商： | MAX192 |
M
Low-Power, 8-Channel,
S erial 10-Bit ADCs
6
________________________________________________________________________________________________
+5V
3k
C
LOAD
DGND
DOUT
C
LOAD
DGND
3k
DOUT
a. High-Z to V
OH
and V
OL
to V
OH
b. High-Z to V
OL
and V
OH
to V
OL
+5V
3k
C
LOAD
DGND
DOUT
C
LOAD
DGND
3k
DOUT
a V
OH
to High-Z
b V
OL
to High-Z
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disabled Time
_____________________________________________________________Pin Desc ription
PIN
NAME
FUNCTION
1–8
CH0–CH7
Sampling Analog Inputs
9, 13
AGND
Analog Ground. Also IN- Input for single-enabled conversions. Connect both AGND pins to
analog ground.
10
S———N
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX192 down to 10μA (max) supply cur-
rent, otherwise the MAX192 is fully operational. Pulling SHDN high puts the reference-buffer amplifi-
er in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in external
compensation mode.
11
VREF
Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier.
Add a 4.7μF capacitor to ground when using external compensation mode. Also functions as an
input when used with a precision external reference.
12
REFADJ
Reference-Buffer Amplifier Input. To disable the reference-buffer amplifier, tie REFADJ to V
DD
.
14
DGND
Digital Ground
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when –—is
high.
15
DOUT
16
SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX192 begins the A/D
conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses
(external mode).
17
DIN
Serial Data Input. Data is clocked in at the rising edge of SCLK.
Active-Low Chip Select. Data will not be clocked into DIN unless –—is low. When –—is high,
DOUT is high impedance.
18
C—
19
SCLK
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also
sets the conversion speed. (Duty cycle must be 45% to 55%.)
20
V
DD
Positive Supply Voltage, +5V ±5%
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