參數(shù)資料
型號(hào): MAX19192ETI+T
廠商: Maxim Integrated Products
文件頁數(shù): 3/22頁
文件大?。?/td> 0K
描述: IC ADC 8BIT DUAL 10MSPS 28-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 8
采樣率(每秒): 10M
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 1.67W
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 28-TQFN-EP(5x5)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個(gè)單端,單極;2 個(gè)差分,單極
MAX19192
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
______________________________________________________________________________________
11
Detailed Description
The MAX19192 uses a seven-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is 5 clock cycles for channel A and
5.5 clock cycles for channel B.
At each stage, flash ADCs convert the held input volt-
ages into a digital code. The following digital-to-analog
converter (DAC) converts the digitized result back into
an analog voltage, which is then subtracted from the
original held input signal. The resulting error signal is
then multiplied by two, and the product is passed along
to the next pipeline stage where the process is repeat-
ed until the signal has been processed by all stages.
Digital error correction compensates for ADC compara-
tor offsets in each pipeline stage and ensures no miss-
ing codes. Figure 2 shows the MAX19192 functional
diagram.
INA+
INA-
T/H
DIGITAL ERROR CORRECTION
D0–D7
FLASH
ADC
T/H
DAC
-
+
x2
1.5 BITS
STAGE 1
STAGE 2
STAGE 7
Figure 1. Pipeline Architecture—Stage Blocks
INA+
INA-
DEC
/
T/H
INB+
INB-
DEC
/
T/H
/
REFERENCE
SYSTEM AND
BIAS
CIRCUITS
PIPELINE
ADC
A
COM
REFIN
REFN
REFP
CLK
TIMING
OVDD
OGND
MULTIPLEXER
OUTPUT
DRIVERS
POWER
CONTROL
D0–D7
/
VDD
GND
A/B
PD0
PD1
PIPELINE
ADC
B
MAX19192
Figure 2. MAX19192 Functional Diagram
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