1. 參數(shù)資料
    型號(hào): MAX148AEPP
    廠商: MAXIM INTEGRATED PRODUCTS INC
    元件分類: ADC
    英文描述: +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs
    中文描述: 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20
    封裝: PLASTIC, DIP-20
    文件頁(yè)數(shù): 11/24頁(yè)
    文件大?。?/td> 221K
    代理商: MAX148AEPP
    M
    +2.7V to +5.25V, Low-Power, 8-Channel,
    S erial 10-Bit ADCs
    ______________________________________________________________________________________
    11
    Simple Software Interface
    Make sure the CPU’s serial interface runs in master
    mode so the CPU generates the serial clock. Choose a
    clock frequency from 100kHz to 2MHz.
    1) Set up the control byte for external clock mode and
    call it TB1. TB1 should be of the format: 1XXXXX11
    binary, where the Xs denote the particular channel
    and conversion mode selected.
    2) Use a general-purpose I/O line on the CPU to pull
    CS
    low.
    3) Transmit TB1 and, simultaneously, receive a byte
    and call it RB1. Ignore RB1.
    4) Transmit a byte of all zeros ($00 hex) and, simulta-
    neously, receive byte RB2.
    5) Transmit a byte of all zeros ($00 hex) and, simulta-
    neously, receive byte RB3.
    6) Pull
    CS
    high.
    Figure 6 shows the timing for this sequence. Bytes RB2
    and RB3 contain the result of the conversion, padded
    with one leading zero, two sub-LSB bits, and three trail-
    ing zeros. The total conversion time is a function of the
    serial-clock frequency and the amount of idle time
    between 8-bit transfers. To avoid excessive T/H droop,
    make sure the total conversion time does not exceed
    120μs.
    Digital Output
    In unipolar input mode, the output is straight binary
    (Figure 17). For bipolar input mode, the output is twos
    complement (Figure 18). Data is clocked out at the
    falling edge of SCLK in MSB-first format.
    Cloc k Modes
    The MAX148/MAX149 may use either an external
    serial clock or the internal clock to perform the succes-
    sive-approximation conversion. In both clock modes,
    the external clock shifts data in and out of the
    SSTRB
    CS
    SCLK
    DIN
    DOUT
    1
    4
    8
    12
    16
    20
    24
    START
    SEL2 SEL1 SEL0
    UNI/
    BIP
    DIF
    PD1
    PD0
    B9
    B8
    B7
    B6
    B5
    B4
    B3
    B2
    B1
    S0
    S1
    B0
    ACQUISITION
    1.5
    μ
    s
    (f
    SCLK
    = 2MHz)
    IDLE
    FILLED WITH
    ZEROS
    IDLE
    CONVERSION
    t
    ACQ
    A/D STATE
    RB1
    RB2
    RB3
    Figure 6. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with f
    SCLK
    2MHz)
    SEL2
    SEL1
    SEL0
    CH0
    CH1
    CH2
    CH3
    CH4
    CH5
    CH6
    CH7
    0
    0
    0
    +
    0
    0
    1
    +
    0
    1
    0
    +
    0
    1
    1
    +
    1
    0
    0
    +
    1
    0
    1
    +
    1
    1
    0
    +
    1
    1
    1
    +
    Table 3. Channel Selection in Differential Mode (SGL/
    DIF
    = 0)
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