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參數(shù)資料
| 型號： | MAX148 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs(8通道，133ksps，串行10位A/D轉(zhuǎn)換器) |
| 中文描述： | +2.7V至+5.25V、低功耗、8通道、串行10位ADC |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 200K |
| 代理商： | MAX148 |
M
+2.7V, Low-Power, 8-Channel,
S erial 10-Bit ADC
______________________________________________________________________________________
15
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. As shown in Table 6, PD1 and
PD0 also specify the clock mode. When software shut-
down is asserted, the ADC will continue to operate in
the last specified clock mode until the conversion is
complete. Then the ADC powers down into a low quies-
cent-current state. In internal clock mode, the interface
remains active and conversion results may be clocked out
after the MAX148 has entered a software power-down.
The first logical 1 on DIN will be interpreted as a start bit,
and powers up the MAX148. Following the start bit, the
data input word or control byte also determines clock
mode and power-down states. For example, if the DIN
word contains PD1 = 1, then the chip will remain pow-
ered up. If PD0 = PD1 = 0, a power-down will resume
after one conversion.
Hardware Power-Down
Pulling
SHDN
low places the converter in hardware
power-down. Unlike the software power-down mode, the
conversion is not completed; it stops coincidentally with
SHDN
being brought low.
SHDN
also controls the clock
frequency in internal clock mode. Letting
SHDN
float sets
the internal clock frequency to 1.8MHz. When returning
to normal operation with
SHDN
floating, there is a t
RC
delay of approximately 2M
x C
L
, where C
L
is the
capacitive loading on the
SHDN
pin. Pulling
SHDN
high
sets the internal clock frequency to 225kHz. This fea-
ture eases the settling-time requirement for the refer-
ence voltage.
External Referenc e
An external reference is required for the MAX148. The
reference voltage range is 1V to V
DD
.
At VREF, the input impedance is a minimum of 18k
for
DC currents. During a conversion, the reference must
be able to deliver up to 250μA DC load current and
have an output impedance of 10
or less. If the refer-
ence has higher output impedance or is noisy, bypass
it close to the VREF pin with a 0.1μF capacitor.
10,000
1000
0.1
0.1
1
10
100
1k
10k 100k 1M
100
10
1
CONVERSIONS PER CHANNEL PER SECOND (Hz)
D
μ
A
V
DD =
V
REF
= 3.0V
C
LOAD
= 100pF
CODE = 101010100000
M
8 CHANNELS
1 CHANNEL
PD1
PD0
DEVICE MODE
1
1
0
1
0
1
External Clock Mode
Internal Clock Mode
Unassigned
0
0
Power-Down Mode
SHDN
STATE
DEVICE
MODE
INTERNAL CLOCK
FREQUENCY
1
Enabled
Enabled
225kHz
1.8MHz
Floating
0
Power-Down
N/A
Table 4. Software Power-Down and
Clock Mode
Table 5. Hard-Wired Power-Down and
Internal Clock Frequency
UNIPOLAR MODE
BIPOLAR MODE
Full Scale
Zero Scale
Positive
Full Scale
VREF/2
+ COM
Zero
Scale
Negative
Full Scale
-VREF/2
+ COM
VREF + COM
COM
COM
Table 6. Full Scale and Zero Scale
Figure 13. Average Supply Current vs. Conversions per
Sample per Second in Power-Down
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