參數(shù)資料
型號(hào)： MAX1434ECQ+D
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 18/22頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT 50MSPS 100-TQFP
標(biāo)準(zhǔn)包裝： 90
位數(shù)： 10
采樣率（每秒）： 50M
數(shù)據(jù)接口： LVDS，串行
轉(zhuǎn)換器數(shù)目： 8
功率耗散（最大）： 882mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： *
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
輸入數(shù)目和類型： 8 個(gè)差分
MAX1434
Octal, 10-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 3.3V, VGND = 0V, external VREFIO = 1.24V, CREFIO = 0.1F, CREFP = 10F, CREFN = 10F,
fCLK = 50MHz (50% duty cycle), VDT = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (Note 8)
Data Valid to CLKOUT Rise/Fall
tOD
Figure 5 (Note 9)
(tSAMPLE /20)
- 0.15
(tSAMPLE /20)
+ 0.15
ns
CLKOUT Output-Width High
tCH
Figure 5
tSAMPLE /10
ns
CLKOUT Output-Width Low
tCL
Figure 5
tSAMPLE /10
ns
FRAME Rise to CLKOUT Rise
tCF
Figure 4 (Note 9)
(tSAMPLE /20)
- 0.15
(tSAMPLE /20)
+ 0.15
ns
Sample CLK Rise to FRAME Rise
tSF
Figure 4 (Note 9)
(3tSAMPLE /5)
+ 1.1
(3tSAMPLE /5)
+ 2.6
ns
Crosstalk
(Note 4)
-94
dB
Gain Matching
CGM
fIN = 5.3MHz (Note 4)
±0.1
dB
Phase Matching
CPM
fIN = 5.3MHz (Note 4)
±0.25
Degrees
Note 2: Specifications at TA ≥ +25°C are guaranteed by production testing. Specifications at TA < +25°C are guaranteed by design
and characterization and not subject to production testing.
Note 3: All capacitances are between the indicated pin and GND, unless otherwise noted.
Note 4: See definition in the
Parameter Definitions section at the end of this data sheet.
Note 5: See the
Common-Mode Output (CMOUT) section.
Note 6: Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AVDD directly to disable the inter-
nal bandgap reference and enable external reference mode.
Note 7: Measured using CREFP to GND = 1F and CREFN to GND = 1F. tENABLE time may be lowered by using smaller capacitor values.
Note 8: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level.
Note 9: Guaranteed by design and characterization. Not subject to production testing.
Typical Operating Characteristics
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 3.3V, VGND = 0V, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 50MHz
(50% duty cycle), VDT = 0V, CLOAD = 10pF, TA = +25°C, unless otherwise noted.)
FFT PLOT
(16,384-POINT DATA RECORD)
MAX1434
toc01
FREQUENCY (MHz)
AMPLITUDE
(dBFS)
0
-10
-20
-30
-40
-50
-70
-60
-80
-100
-90
510
15
020
25
HD2
HD3
fCLK = 50.1523789MHz
fIN = 5.304814MHz
AIN = -0.5dBFS
SNR = 61.146dB
SINAD = 61.139dB
THD = -89.316dBc
SFDR = 84.455dBc
0
-10
-20
-30
-40
-50
-70
-60
-80
-100
-90
510
15
020
25
FFT PLOT
(16,384-POINT DATA RECORD)
MAX1434
toc02
FREQUENCY (MHz)
AMPLITUDE
(dBFS)
fCLK = 50.152379MHz
fIN = 24.0997119MHz
AIN = -0.5dBFS
SNR = 61.118dB
SINAD = 61.112dB
THD = -91.363dBc
SFDR = 85.069dBc
HD3
HD2
CROSSTALK
(16,384-POINT DATA RECORD)
MAX1434
toc03
FREQUENCY (MHz)
AMPLITUDE
(dBFS)
0
-10
-20
-30
-40
-50
-70
-60
-80
-100
-90
510
15
020
25
MEASURED ON CHANNEL 1,
WITH INTERFERING SIGNAL
ON CHANNEL 2
fIN(IN1) = 5.304814MHz
fIN(IN2) = 24.0997119MHz
CROSSTALK = 94dB
fIN(IN2)
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