參數(shù)資料
型號： MAX1403CAI+
廠商： Maxim Integrated Products
文件頁數(shù)： 21/36頁
文件大?。?/td> 0K
描述： IC ADC 18BIT LP 28-SSOP
產(chǎn)品培訓(xùn)模塊： MAX11200 ADC
Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 46
位數(shù)： 18
采樣率（每秒）： 480
數(shù)據(jù)接口： QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 21.45mW
電壓電源： 模擬和數(shù)字
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 管件
輸入數(shù)目和類型： 3 個差分，單極；3 個差分，雙極；5 個偽差分，單極；5 個偽差分，雙極
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
28
______________________________________________________________________________________
Offset-Correction DAC
The MAX1403 provides a coarse (3-bit plus sign) offset-
correction DAC at the modulator input. Use this DAC to
remove the offset component in the input signal, allow-
ing the ADC to operate on a more sensitive range. The
DAC offsets up to ±116.7% of the selected range in
±16.7% increments for unipolar mode, and up to
±58.3% of the selected range in ±8.3% increments for
bipolar mode. When a DAC value of 0 is selected, the
DAC is completely disconnected from the modulator
inputs and does not contribute any noise. Figures 8
and 9 show the effect of the DAC codes on the input
range and transfer function.
Clock Oscillator
The clock oscillator may be used with an external crystal
(or resonator) connected between CLKIN and CLKOUT,
or may be driven directly by an external oscillator at
CLKIN with CLKOUT left unconnected. In normal oper-
ating mode, the MAX1403 is specified for operation with
CLKIN at either 1.024MHz (CLK = 0) or 2.4576MHz
(CLK = 1, default). When operated at these frequencies,
the device may be programmed to produce frequency
response nulls at the local line frequency (either 60Hz or
50Hz) and the associated line harmonics.
In standby mode (STBY = 1) all circuitry, with the
exception of the serial interface and the clock oscillator,
is powered down. The interface consumes minimal
power with a static SCLK. Enter power-down mode
(including the oscillator) by setting the FULLPD bit in
the special-function register. When exiting a full-power
shutdown, perform a hardware reset or a software reset
after the master clock signal is established (typically
10ms when using the on-board oscillator with an exter-
nal crystal) to ensure that any potentially corrupted reg-
isters are cleared.
It is often helpful to use higher-frequency crystals or
resonators, especially for surface-mount applications
where the result may be reduced PC board area for the
oscillator component and a lower price or better com-
ponent availability. Also, it may be necessary to oper-
ate the part with a clock source whose duty cycle is not
close to 50%. In either case, the MAX1403 can operate
with a master clock frequency of up to 5MHz, and
includes an internal divide-by-2 prescaler to restore the
internal clock frequency to a range of up to 2.5MHz
with a 50% duty cycle. To activate this prescaler, set
the X2CLK bit in the control registers. Note that using
CLKIN frequencies above 2.5MHz in combination with
the X2CLK mode will result in a small increase in digital
supply current.
DAC CODE
D3:
D2:
D1:
D0:
INPUT
VOLTAGE
RANGE
(VREF = 1.25V
PGA = 000)
-7
1
-6
1
0
-5
1
0
1
-4
1
0
-3
1
0
1
-2
1
0
1
0
-1
1
0
1
0
+1
0
1
+2
0
1
0
+3
0
1
+4
0
1
0
+5
0
1
0
1
+6
0
1
0
+7
0
1
2.708V
2.50V
2.292V
2.083V
1.875V
1.667V
1.458V
1.25V
1.042V
0.833V
0.625V
0.416V
0.208V
0V
-0.208V
-0.416V
-0.625V
-0.833V
-1.042V
-1.25V
-1.458V
-1.667V
-1.875V
-2.083V
-2.292V
-2.50V
-2.708V
13/6 VREF/2PGA
2 VREF/2PGA
11/6 VREF/2PGA
10/6 VREF/2PGA
9/6 VREF/2PGA
8/6 VREF/2PGA
7/6 VREF/2PGA
VREF/2PGA
5/6 VREF/2PGA
4/6 VREF/2PGA
3/6 VREF/2PGA
2/6 VREF/2PGA
1/6 VREF/2PGA
0
-1/6 VREF/2PGA
-2/6 VREF/2PGA
-3/6 VREF/2PGA
-4/6 VREF/2PGA
-5/6 VREF/2PGA
-VREF/2PGA
-7/6 VREF/2PGA
-8/6 VREF/2PGA
-9/6 VREF/2PGA
-10/6 VREF/2PGA
-11/6 VREF/2PGA
-2 VREF/2PGA
-13/6 VREF/2PGA
MAXIMUM
INPUT
MINIMUM
INPUT
(U/B
= 1)
MINIMUM
INPUT
(U/B
= 0)
Figure 9. Input Voltage Range vs. DAC Code
ZERO-SCALE 2621
MIDSCALE 131072
NEGATIVE DAC STEP
SHIFTS THE TRANSFER
FUNCTION TOWARD
THE POSITIVE RAIL.
PGA = 3
DAC = 0
PGA = 0
DAC = 0
PGA = 3
DAC = +3
MAX CODE 262144
FULL-SCALE 259522
INPUT VOLTAGE RANGE
CODE
(V
AIN
-)-V
REF
AGND
(V
AIN
-)
-
V
REF
/8
-
V
REF
/16
(V
AIN
-)
-
V
REF
/8
-
V
REF
/16
(V
AIN
-)
-
V
REF
/8
(V
AIN
-)
+
V
REF
/8
V+
(V
AIN
-)
+
V
REF
(V
AIN-
)
Figure 8. Effect of PGA and DAC Codes on the Bipolar Transfer
Function
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參數(shù)描述
MAX1403CAI+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit 5Ch 4.8ksps 1.25V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1403CAI+T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit 5Ch 4.8ksps 1.25V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1403CAI-T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1403EAI 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1403EAI+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit 5Ch 4.8ksps 1.25V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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