參數(shù)資料
型號(hào): MAX1402EAI+T
廠(chǎng)商: Maxim Integrated Products
文件頁(yè)數(shù): 10/38頁(yè)
文件大?。?/td> 0K
描述: IC ADC 18BIT LP 28-SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 18
采樣率(每秒): 480
數(shù)據(jù)接口: QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 34mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 3 個(gè)差分,單極;3 個(gè)差分,雙極;5 個(gè)偽差分,單極;5 個(gè)偽差分,雙極
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
18
______________________________________________________________________________________
Special Function Register (Write-Only)
MDOUT: (Default = 0) Modulator Out Bit. MDOUT = 0
enables data readout on the DOUT pin, the normal con-
dition for the serial interface. MDOUT = 1 changes the
function of the DOUT and INT pins, providing raw, sin-
gle-bit modulator output instead of the normal serial-
data interface output. This allows custom filtering
directly on the modulator output, without going through
the on-chip digital filter. The INT pin provides a clock to
indicate when the modulator data at DOUT should be
sampled (falling edge of INT). Note that in this mode,
the on-chip digital filter continues to operate normally.
When MDOUT is returned to 0, valid data may be
accessed through the normal serial-interface read
operation.
FULLPD: (Default = 0) Complete Power-Down Bit.
FULLPD = 1 forces the part into a complete power-down
condition, which includes the clock oscillator. The serial
interface continues to operate. The part requires a hard-
ware reset to recover correctly from this condition.
Note: Changing the reserved bits in the special-func-
tion register from the default status of all 0s will select
one of the reserved modes and the part will not operate
as expected. This register is a write-only register.
However, in the event that this register is mistakenly
read, clock 24 bits of data out of the part to restore it to
the normal interface-idle state.
Transfer-Function Registers
The three transfer-function registers control the method
used to map the input voltage to the output codes. All
of the registers have the same format. The mapping of
control registers to associated channels depends on
the mode of operation and is affected by the state of
M1, M0, DIFF, and SCAN (Tables 8, 9, and 10).
Table 4. SCAN Mode Scanning
Sequences (SCAN = 1)
Table 5. Available Input Channels
(SCAN = 0)
Note: All other combinations reserved.
Special Function Register (Write-Only)
Transfer-Function Register
G2
D3
0
Defaults
G1
PGA GAIN CONTROL
D0
Name
OFFSET CORRECTION
0
D2
0
D1
G0
0
U/B
0
FUNCTION
0
M1
0
M0
0
1
AIN1–AIN6, AIN2–AIN6, AIN3–AIN6,
AIN4–AIN6, AIN5–AIN6, CALOFF,
CALGAIN
0
1
0
AIN1–AIN2, AIN3–AIN4, AIN5–AIN6
1
AIN1–AIN6, AIN2–AIN6, AIN3–AIN6,
AIN4–AIN6, AIN5–AIN6, CALOFF,
CALGAIN
AIN1–AIN6, AIN2–AIN6, AIN3–AIN6,
AIN4–AIN6, AIN5–AIN6
0
1
0
AIN1–AIN2, AIN3–AIN4, AIN5–AIN6,
CALOFF, CALGAIN
1
AIN1–AIN2, AIN3–AIN4, AIN5–AIN6,
CALOFF, CALGAIN
1
DIFF
SEQUENCE
First Bit (MSB)
(LSB)
0
Defaults
RESERVED BITS
0
MDOUT
0
FULLPD
Name
0
RESERVED BITS
0
FUNCTION
First Bit (MSB)
(LSB)
0
M1
0
M0
0
1
CALOFF
0
1
0
AIN1–AIN2, AIN3–AIN4, AIN5–AIN6
1
CALGAIN
AIN1–AIN6, AIN2–AIN6,
AIN3–AIN6, AIN4–AIN6
0
1
0
CALGAIN
1
CALOFF
1
DIFF
AVAILABLE CHANNELS
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