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參數(shù)資料
| 型號： | MAX1364MEUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 22/25頁 |
| 文件大小： | 0K |
| 描述： | IC SYSTEM MON 12BIT 4CH 10-UMAX |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 133k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 444.4mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極；2 個差分，單極；2 個差分，雙極 |
Typical Operating Characteristics
(VDD = 3.3V (MAX1363), VDD = 5V (MAX1364), fSCL = 1.7MHz, external clock, fSAMPLE = 94.4ksps, single-ended, unipolar,
TA = +25°C, unless otherwise noted.)
MAX1363/MAX1364
4-Channel, 12-Bit System Monitors with Programmable
Trip Window and SMBus Alert Response
6
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX1363), VDD = 4.5V to 5.5V (MAX1364), VREF = 2.048V (MAX1363), VREF = 4.096V (MAX1364), CREF =
0.1F, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Note 1:
Devices configured for unipolar single-ended inputs.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain and offset have
been calibrated.
Note 3:
Offset nulled.
Note 4:
Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period.
Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 5:
The throughput rate of the I
2C bus is limited to 94.4ksps. The MAX1363/MAX1364 can perform conversions up to 133ksps
in monitor mode when not reading back results on the I
2C bus.
Note 6:
A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7:
The absolute input-voltage range for the analog inputs (AIN0–AIN3) is from GND to VDD.
Note 8:
When the internal reference is configured to be available at AIN3/REF (SEL[2:1] = 11), decouple AIN3/REF to GND with a
0.01F capacitor.
Note 9:
ADC performance is limited by the converter’s noise floor, typically 300VP-P.
Note 10: Maximum conversion throughput in internal clock mode when the data is not clocked out.
Note 11: For the MAX1363, PSRR is measured as
and for the MAX1364, PSRR is measured as
Note 12: CB = total capacitance of one bus line in pF.
Note 13: fSCLH must meet the minimum clock low time plus the rise/fall times.
Note 14: A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region of SCL’s
falling edge.
VV
V
VV
FS
N
REF
(.
)
( .
)
( ..
)
55
45
21
55
45
[]×
VV
V
VV
FS
N
REF
(.
)
( .
)
(.
.
)
36
27
21
36
27
[]×
-180
-160
-140
-120
-100
-80
-60
0
1020304050
FFT PLOT
MAX1363/64
toc03
FREQUENCY (kHz)
AMPLITUDE
(dBc)
fSAMPLE = 94.4ksps
fIN = 10kHz
-0.5
-0.2
-0.4
-0.3
0.2
0.1
-0.1
0
0.3
0.5
0
4000
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
MAX1363/64
toc01
DIGITAL OUTPUT CODE
DNL
(LSB)
1000 1500
500
2000 2500 3000 3500
0.4
-1.0
-0.4
-0.6
-0.8
-0.2
0
0.2
0.4
0.6
0.8
1.0
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
MAX1363/64
toc02
DIGITAL OUTPUT CODE
INL
(LSB)
0
4000
1000 1500
500
2000 2500 3000 3500
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