參數(shù)資料
型號: MAX1363EUB+T
廠商: Maxim Integrated Products
文件頁數(shù): 20/25頁
文件大?。?/td> 0K
描述: IC SYSTEM MON 12BIT 4CH 10-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
位數(shù): 12
采樣率(每秒): 133k
數(shù)據(jù)接口: I²C,串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 444.4mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個單端,單極;4 個單端,雙極;2 個差分,單極;2 個差分,雙極
MAX1363/MAX1364
4-Channel, 12-Bit System Monitors with Programmable
Trip Window and SMBus Alert Response
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX1363), VDD = 4.5V to 5.5V (MAX1364), VREF = 2.048V (MAX1363), VREF = 4.096V (MAX1364), CREF =
0.1F, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Internal reference
660
1600
fSAMPLE =
133ksps,
monitor mode
(Note 10)
External reference
436
1350
Internal reference
900
1150
fSAMPLE =
94.4ksps,
external clock External reference
670
900
Internal reference
530
fSAMPLE =
40ksps,
internal clock
External reference
230
Internal reference
380
fSAMPLE =
10ksps,
internal clock
External reference
60
Internal reference
330
MAX1363
fSAMPLE =
1ksps,
internal clock
External reference
6
Internal reference
660
1600
fSAMPLE =
133ksps,
monitor mode
(Note10)
External reference
436
1350
Internal reference
900
1150
fSAMPLE =
94.4ksps,
external clock External reference
670
900
Internal reference
530
fSAMPLE =
40ksps,
internal clock
External reference
230
Internal reference
380
fSAMPLE =
10ksps,
internal clock
External reference
60
Internal reference
330
Supply Current
IDD
MAX1364
fSAMPLE =
1ksps, internal
clock
External reference
6
A
Internal reference on
333
Shutdown Current
Internal reference off
0.5
10
A
Power-Supply Rejection Ratio
PSRR
Full-scale input (Note 11)
±0.01
±0.5
LSB/V
TIMING CHARACTERISTICS FOR FAST MODE (Figures 1a, 2)
Serial Clock Frequency
fSCL
400
kHz
Bus Free Time Between a
STOP (P) and a
START (S) Condition
tBUF
1.3
s
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