
MAX13101E/MAX13102E/
MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
4
Maxim Integrated
TIMING CHARACTERISTICS
(VCC = +1.65V to +5.5V, VL = +1.2V to VCC, EN = VL (MAX13101E/MAX13102E/MAX13103E), MULT = VL or GND (MAX13108E),
TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +1.65V, VL = +1.2V, TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I/O VL _ Rise Time
tRVL
RS = 50
Ω, CI/OVL_ = 15pF, tRISE ≤ 3ns,
(Figures 2a, 2b)
15
ns
I/O VL _ Fall Time
tFVL
RS = 50
Ω, CI/OVL_ = 15pF, tFALL ≤ 3ns,
(Figures 2a, 2b)
15
ns
I/O VCC_ Rise Time
tRVCC
RS = 50
Ω, CI/OVCC_ = 50pF, tRISE ≤ 3ns,
(Figures 1a, 1b)
15
ns
I/O VCC_ Fall Time
tFVCC
RS = 50
Ω, CI/OVCC_ = 50pF, tFALL ≤ 3ns,
(Figures 1a, 1b)
15
ns
Propagation Delay
(Driving I/O VL _)
tPVL-VCC
RS = 50
Ω, CI/OVCC_ = 50pF, tRISE ≤ 3ns,
(Figures 1a, 1b)
20
ns
Propagation Delay
(Driving I/O VCC_)
tPVCC-VL
RS = 50
Ω, CI/OVL_ = 15pF, tRISE ≤ 3ns,
(Figures 2a, 2b)
20
ns
Channel-to-Channel Skew
tSKEW
RS = 50
Ω, CI/OVCC_ = 50pF, CI/OVL_ =
15pF, tRISE
≤ 3ns
5ns
Part-to-Part Skew
tPPSKEW
RS = 50
Ω, CI/OVCC_ = 50pF, CI/OVL_ =
15pF, tRISE
≤ 3ns, ΔTA = +20°C (Notes 3, 4)
10
ns
Propagation Delay from
I/O VL _ to I/O VCC_ After EN
tEN-VCC
CI/OVCC_ = 50pF (Figure 3)
1
s
Propagation Delay from
I/O VCC_ to I/O VL _ After EN
tEN-VL
CI/OVL_ = 15pF (Figure 4)
1
s
Maximum Data Rate
RSOURCE = 50
Ω, CI/OVCC_ = 50pF,
CI/OVL_ = 15pF, tRISE
≤ 3ns
20
Mbps
Note 1: All units are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design
and not production tested.
Note 2: For normal operation, ensure that VL < (VCC + 0.3V). During power-up, VL > (VCC + 0.3V) does not damage the device.
Note 3: VCC from device 1 must equal VCC of device 2. VL from device 1 must equal VL of device 2.
Note 4: Guaranteed by design, not production tested.