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參數(shù)資料
| 型號： | MAX1304ECM/V+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 4000KSPS 8CH 48LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 250 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 3.65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.82W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個單端，單極 |
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MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
______________________________________________________________________________________
15
Detailed Description
The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–
MAX1314 are 12-bit ADCs. The devices offer 8, 4, or 2
independently selectable input channels, each with
dedicated T/H circuitry. Simultaneous sampling of all
active channels preserves relative phase information
making these devices ideal for motor control and power
monitoring. Three input ranges are available, 0 to +5V,
±5V and ±10V. The 0 to +5V devices provide ±6V fault-
tolerant inputs. The ±5V and ±10V devices provide
±16.5V fault-tolerant inputs. Two-channel conversion
results are available in 0.9s. Conversion results from
all eight channels are available in 1.98s. The 8-chan-
nel throughput is 456ksps per channel. Internal or
external reference and clock capability offer great flexi-
bility, and ease of use. A write-only configuration regis-
ter can mask out unused channels and a shutdown
feature reduces power. A 20MHz, 12-bit, parallel data
bus outputs the conversion results. Figure 2 shows the
functional diagram of these ADCs.
100pF
DEVICE PIN
VDD
IOL = 1.6mA
IOH = 0.8mA
1.6V
Figure 1. Digital Load Test Circuit
Pin Description (continued)
PIN
MAX1304
MAX1308
MAX1312
MAX1305
MAX1309
MAX1313
MAX1306
MAX1310
MAX1314
NAME
FUNCTION
44
CS
Chip-Select Input. Pulling CS low activates the digital interface. Forcing CS high
places D0–D11 in high-impedance mode.
45
CONVST
Conversion Start Input. Driving CONVST high initiates the conversion process.
The analog inputs are sampled on the rising edge of CONVST.
46
CLK
External Clock Input. For external clock operation, connect INTCLK/EXTCLK to
AGND and drive CLK with an external clock signal from 100kHz to 20MHz. For
internal clock operation, connect INTCLK/EXTCLK to AVDD and connect CLK
to DGND.
47
SHDN
Shutdown Input. Driving SHDN high initiates device shutdown. Connect SHDN
to DGND for normal operation.
48
CHSHDN
Active-Low Analog-Input Channel-Shutdown Input. Drive CHSHDN low to
power down analog inputs that are not selected for conversion in the
configuration register. Drive CHSHDN high to power up all analog input
channels regardless of whether they are selected for conversion in the
configuration register. See the Channel Shutdown (CHSHDN) section for more
information.
—
9, 10,
11, 12
7, 8, 9,
10, 11, 12
I.C.
Internally connected. Connect I.C. to AGND.
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| MAX13050ASA+T | 功能描述:CAN 接口集成電路 CAN Transceiver w/80V Fault Protect RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
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