參數(shù)資料
型號: MAX1302AEUG+T
廠商: Maxim Integrated Products
文件頁數(shù): 19/31頁
文件大?。?/td> 0K
描述: IC ADC 16BIT SRL 115KSPS 24TSSOP
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 16
采樣率(每秒): 115k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.11W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個(gè)單端,單極;8 個(gè)單端,雙極;4 個(gè)差分,單極;4 個(gè)差分,雙極
MAX1302
Bridge Application
The MAX1302 converts 1kHz signals more accurately
than a similar sigma-delta converter that might be con-
sidered in bridge applications. The input impedance of
the MAX1302, in combination with the current-limiting
resistors, can affect the gain of the MAX1302. In many
applications this error is acceptable, but for applica-
tions that cannot tolerate this error, the MAX1302 inputs
can be buffered (Figure 20). Connect the bridge to a
low-offset differential amplifier and then the true differ-
ential inputs of the MAX1302. Larger excitation voltages
take advantage of more of the ±VREF/2 differential input
voltage range. Select an input voltage range that
matches the amplifier output. Be aware of the amplifier
offset and offset-drift errors when selecting an appro-
priate amplifier.
Dynamically Adjusting the Input Range
Software control of each channel’s analog input range
and the unipolar endpoint overlap specification make it
possible for the user to change the input range for a
channel dynamically and improve performance in some
applications. Changing the input range results in a
small LSB step-size over a wider output voltage range.
For example, by switching between a -VREF/2 to 0V
range and a 0V to VREF/2 range, an LSB is:
but the input voltage range effectively spans from
-VREF/2 to +VREF/2 (FSR = +VREF).
Layout, Grounding, and Bypassing
Careful PCB layout is essential for best system perfor-
mance. Boards should have separate analog and digital
ground planes and ensure that digital and analog sig-
nals are separated from each other. Do not run analog
and digital (especially clock) lines parallel to one anoth-
er, or digital lines underneath the device package.
Figure 1 shows the recommended system ground con-
nections. Establish an analog ground point at AGND1
and a digital ground point at DGND. Connect all analog
grounds to the star analog ground. Connect the digital
grounds to the star digital ground. Connect the digital
ground plane to the analog ground plane at one point.
For lowest noise operation, make the ground return to
the star ground’s power-supply low impedance and as
short as possible.
High-frequency noise in the AVDD1 power supply
degrades the ADC’s high-speed comparator perfor-
mance. Bypass AVDD1 to AGND1 with a 0.1F ceramic
surface-mount capacitor. Make bypass capacitor con-
nections as short as possible.
Parameter Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. This straight line is either a
best straight-line fit or a line drawn between the end-
points of the transfer function once offset and gain
errors have been nullified. The MAX1302 INL is mea-
sured using the endpoint method.
()
,.
VV
REF
2
65 536
4 096
×
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
26
______________________________________________________________________________________
REF
REFCAP
AGND1
4.096V
BANDGAP
REFERENCE
5k
1x
SAR
ADC REF
4.096V
1.0
F
VRCTH
MAX1302
AVDD1
MAX6341
V+
1.0
F
OUT
GND
IN
Figure 18. External Reference Operation
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