參數(shù)資料
型號: MAX1297ACEG+T
廠商: Maxim Integrated Products
文件頁數(shù): 19/19頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 265KSPS 24-QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 12
采樣率(每秒): 265k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 667mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-QSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,單極;2 個單端,雙極;1 個偽差分,單極;1 個偽差分,雙極
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________________________________________________________________________________
9
BIT
PD1, PD0
0
D7, D6
PD1 and PD0 select the various clock and power-down modes.
Full Power-Down Mode. Clock mode is unaffected.
D5
ACQMOD
ACQMOD = 0: Internal Acquisition Mode
ACQMOD = 1: External Acquisition Mode
NAME
FUNCTIONAL DESCRIPTION
0
1
0
Standby Power-Down Mode. Clock mode is unaffected.
0
1
Normal Operation Mode. External clock mode selected.
1
Normal Operation Mode. Internal clock mode selected.
D4
SGL/DIF
SGL/DIF = 0: Pseudo-Differential Analog Input Mode
SGL/DIF = 1: Single-Ended Analog Input Mode
In single-ended mode, input signals are referred to COM. In differential mode, the voltage difference
between two channels is measured (Tables 2, 4).
D3
UNI/BIP
UNI/BIP = 0: Bipolar Mode
UNI/BIP = 1: Unipolar Mode
In unipolar mode, an analog input signal from 0V to VREF can be converted; in bipolar mode, the
signal can range from -VREF/2 to +VREF/2.
D2, D1, D0
A2, A1, A0
Address bits A2, A1, A0 select which of the 6/2 (MAX1295/MAX1297) channels is to be converted
(Tables 2, 3).
Table 1. Control-Byte Functional Description
the analog inputs. This configuration is pseudo-differ-
ential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within ±0.5 LSB
(±0.1 LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1F capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. At the
end of the acquisition interval, the T/H switch opens,
retaining charge on CHOLD as a sample of the signal
at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLD from the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at
the comparator’s positive input. The capacitive digital-
to-analog converter (DAC) adjusts during the remain-
Figure 3a. MAX1295 Simplified Input Structure
Figure 3b. MAX1297 Simplified Input Structure
CH0
CH1
CH2
CH3
CH4
CH5
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
800
CHOLD
HOLD
12-BIT CAPACITIVE DAC
VREF
ZERO
COMPARATOR
+
12pF
SINGLE-ENDED MODE: IN+ = CH0–CH5, IN- = COM
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1 AND CH2/CH3, AND CH4/CH5
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
CH0
CH1
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
800
CHOLD
HOLD
12-BIT CAPACITIVE DAC
VREF
ZERO
COMPARATOR
+
12pF
SINGLE-ENDED MODE: IN+ = CH0–CH1, IN- = COM
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIR
CH0/CH1
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
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MAX1297AEEG+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 2Ch 265ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1297AEEG+T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 2Ch 265ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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