參數(shù)資料
型號: MAX1296ACEG+T
廠商: Maxim Integrated Products
文件頁數(shù): 6/19頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 420KSPS 24-QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 12
采樣率(每秒): 420k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 762mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-QSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,單極;2 個單端,雙極;1 個偽差分,單極;1 個偽差分,雙極
MAX1294/MAX1296
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
14
______________________________________________________________________________________
Input Format
The control bit sequence is latched into the device on
pins D7–D0 during a write command. Table 4 shows
the control-byte format.
Output Data Format
The 12-bit-wide output format for both the MAX1294/
MAX1296 is binary in unipolar mode and two’s comple-
ment in bipolar mode. CS, RD, WR, INT, and the 12 bits
of output data can interface directly to a 16-bit data bus.
When reading the output data, CS and RD must be low.
Applications Information
Power-On Reset
When power is first applied, internal power-on reset cir-
cuitry activates the MAX1294/MAX1296 in external clock
mode and sets INT high. After the power supplies stabi-
lize, the internal reset time is 10s; no conversions
should be attempted during this phase. When using the
internal reference, 500s is required for VREF to stabilize.
Internal and External Reference
The MAX1294/MAX1296 can be used with an internal
or external reference voltage. An external reference
can be connected directly to REF or REFADJ.
An internal buffer is designed to provide +2.5V at REF for
both devices. The internally trimmed +1.22V reference is
buffered with a +2.05V/V gain.
Internal Reference
The full-scale range with the internal reference is +2.5V
with unipolar inputs and ±1.25V with bipolar inputs. The
internal reference buffer allows for small adjustments
(±100mV) in the reference voltage (Figure 7).
Note: The reference buffer must be compensated with
an external capacitor (4.7F min) connected between
REF and GND to reduce reference noise and switching
spikes from the ADC. To further minimize reference
noise, connect a 0.01F capacitor between REFADJ
and GND.
External Reference
With the MAX1294/MAX1296, an external reference can
be placed at either the input (REFADJ) or the output
(REF) of the internal-reference buffer amplifier.
Using the REFADJ input makes buffering the external
reference unnecessary. The REFADJ input impedance
is typically 17k
.
When applying an external reference to REF, disable the
internal reference buffer by connecting REFADJ to VDD.
The DC input resistance at REF is 25k
. Therefore, an
external reference at REF must deliver up to 200A DC
load current during a conversion and have an output
impedance less than 10
. If the reference has higher
output impedance or is noisy, bypass it close to the REF
pin with a 4.7F capacitor.
Power-Down Modes
To save power, place the converter in a low-current
shutdown state between conversions. Select standby
mode or shutdown mode using bits D6 and D7 of the
control byte (Tables 1 and 4). In both software power-
down modes, the parallel interface remains active, but
the ADC does not convert.
Standby Mode
While in standby mode, the supply current is typically
1mA. The part powers up on the next rising edge of WR
and is ready to perform conversions. This quick turn-on
time allows the user to realize significantly reduced
power consumption for conversion rates below
420ksps.
D6
D4
D5
PD0
SGL/DIF
ACQMOD
A2
A0
A1
D2
D0
(LSB)
UNI/BIP
PD1
D1
D3
D7
(MSB)
Table 4. Control-Byte Format
VDD = +5V
330k
50k
50k
0.01
F
4.7
F
REFADJ
REF
MAX1294
MAX1296
Figure 7. Reference Adjustment with External Potentiometer
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