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參數(shù)資料
| 型號： | MAX1294BEEI+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 17/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 420KSPS 28-QSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 50 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 420k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 667mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 28-QSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 6 個單端，單極；6 個單端，雙極；3 個偽差分，單極；3 個偽差分，雙極 |
| 產(chǎn)品目錄頁面： | 1396 (CN2011-ZH PDF) |
MAX1294/MAX1296
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________________________________________________________________________________
7
Pin Description
D0
10
INT
11
RD
12
WR
13
CLK
14
D4
6
D3
7
D2
8
D1
9
D5
5
D6
4
1
D7
3
D8
2
D9
1
Three-State Digital I/O Line (D0)
INT goes low when the conversion is complete and output data is ready.
Active-Low Read Select. If CS is low, a falling edge on RD enables the read
operation on the data bus.
Active-Low Write Select. When CS is low in the internal acquisition mode, a rising
edge on WR latches in configuration data and starts an acquisition plus a conver-
sion cycle. When CS is low in external acquisition mode, the first rising edge on WR
ends acquisition and starts a conversion.
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock.
In internal clock mode, connect this pin to either VDD or GND.
Three-State Digital I/O Line (D4)
Three-State Digital I/O Line (D3)
Three-State Digital I/O Line (D2)
Three-State Digital I/O Line (D1)
Three-State Digital I/O Line (D5)
Three-State Digital I/O Line (D6)
Three-State Digital I/O Line (D7)
Three-State Digital Output (D8)
Three-State Digital Output (D9)
GND
19
23
REFADJ
20
24
CH2
—
19
CH1
16
20
CH0
17
21
COM
18
22
CH3
—
18
CH4
—
17
CH5
—
16
CS
15
Analog and Digital Ground
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with
a 0.01F capacitor. When using an external reference, connect REFADJ to VDD to
disable the internal bandgap reference.
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 0
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode
and must be stable to ±0.5 LSB during conversion.
Analog Input Channel 3
Analog Input Channel 4
Analog Input Channel 5
Active-Low Chip Select. When CS is high, digital outputs (INT, D11–D0) are high
impedance.
PIN
MAX1296
MAX1294
NAME
FUNCTION
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1294BEEI+ | 功能描述:模數(shù)轉換器 - ADC 12-Bit 6Ch 420ksps 5.5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1294BEEI+T | 功能描述:模數(shù)轉換器 - ADC 12-Bit 6Ch 420ksps 5.5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1294BEEI-T | 功能描述:模數(shù)轉換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1294EVKIT | 功能描述:數(shù)據(jù)轉換 IC 開發(fā)工具 MAX1294 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX1295ACEI | 功能描述:模數(shù)轉換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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