參數(shù)資料
型號： MAX128
廠商： Maxim Integrated Products, Inc.
英文描述： Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface
中文描述： 多量程、+5V、12位DAS，2線串行接口
文件頁數(shù)： 5/16頁
文件大?。?/td> 124K
代理商： MAX128
M
Multirange, +5V, 12-Bit DAS with
2-Wire S erial Interfac e
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +5V ±5%; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7μF at REF pin; external clock, f
CLK
= 400kHz;
T
A
= T
MIN
to T
MAX
; unless otherwise noted. Typical values are at T
A
= +25°C.)
Input Hysteresis
Input Leakage Current
V
HYS
I
IN
0.05 x V
DD
V
Input Low Threshold Voltage
V
IL
0.3 x V
DD
V
Input High Threshold Voltage
V
IH
0.7 x V
DD
V
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
TIMING CHARACTERISTICS
(V
DD
= +4.75V to +5.25V; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7μF at REF pin; T
A
= T
MIN
to T
MAX
;
unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETERS
SYMBOL
CONDITIONS
22-WIRE FAST MODE
Input Capacitance
DIGITAL OUTPUTS
(SDA)
C
IN
15
pF
(Note 4)
±0.1
±10
μA
V
IN
= 0 or V
DD
Three-State Output Capacitance
C
OUT
15
pF
(Note 4)
Output Low Voltage
V
OL
0.4
0.6
V
I
SINK
= 3mA
I
SINK
= 6mA
SCL Clock Frequency
Hold Time (Repeated)
START Condition
t
HD,STA
0.6
μs
Bus Free Time Between a
STOP and START Condition
t
BUF
1.3
μs
f
SCL
400
kHz
MIN
TYP
MAX
UNITS
Set-Up Time for a Repeated
START Condition
t
SU,STA
0.6
μs
High Period of the SCL Clock
t
HIGH
0.6
μs
Low Period of the SCL Clock
t
LOW
1.3
μs
Rise Time for Both SDA and SCL
Signals (Receiving)
t
R
20 +
0.1 x C
b
300
ns
C
b
= Total capacitance of one bus line in pF
Data Setup Time
t
SU,DAT
100
ns
Data Hold Time
t
HD,DAT
0
0.9
μs
DIGITAL INPUTS
(SDA, SCL)
Fall Time for Both SDA and SCL
Signals (Receiving)
t
F
C
b
= Total capacitance of one bus line in pF
20 +
0.1 x C
b
300
ns
Fall Time for Both SDA and SCL
Signals (Transmitting)
t
F
C
b
= Total capacitance of one bus line in pF
20 +
0.1 x C
b
0.6
250
ns
Set-Up Time for STOP Condition
t
SU,STO
μs
Capacitive Load for Each
Bus Line
C
b
400
pF
Pulse Width of Spike Suppressed
t
SP
0
50
ns
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