參數(shù)資料
型號: MAX1285BCSA+T
廠商: Maxim Integrated Products
文件頁數(shù): 4/15頁
文件大小: 0K
描述: IC ADC 12BIT 300KSPS 8-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 12
采樣率(每秒): 300k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 2.5mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)單端,單極
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
12
______________________________________________________________________________________
SCLK to DOUT valid timing characteristic. Data can be
clocked into the P on SCLK rising edge.
3) Pull CS high at or after the 15th rising clock edge. If CS
remains low, trailing zeros are clocked out after the
LSB.
4) With CS = high, wait the minimum specified time, tCS,
before initiating a new conversion by pulling CS low. If
a conversion is aborted by pulling CS high before the
conversion completes, wait for the minimum acquisition
time, tACQ, before starting a new conversion.
CS must be held low until all data bits are clocked out.
Data can be output in two bytes or continuously, as
shown in Figure 8. The bytes contain the result of the
conversion padded with three leading zeros and three
trailing zeros.
SPI and MICROWIRE
When using SPI or MICROWIRE, set CPOL = 0 and
CPHA = 0. Conversion begins with a CS falling edge.
DOUT goes low, indicating a conversion in progress. Two
consecutive 1-byte reads are required to get the full
twelve bits from the ADC. DOUT output data transitions
on SCLK’s rising edge and is clocked into the following
P on the rising edge.
The first byte contains three leading zeros, and five bits of
conversion result. The second byte contains the remaining
seven bits and one trailing zero. See Figure 11 for con-
nections and Figure 12 for timing.
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1284/MAX1285 require 15 clock cycles
from the P to clock out the 12 bits of data. Figure 13
shows a transfer using CPOL = 0 and CPHA = 1. The
conversion result contains two zeros followed by the 12
bits of data in MSB-first formatted.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap boards
are not recommended. Board layout should ensure that
digital and analog signal lines are separated from each
other. Do not run analog and digital (especially clock)
lines parallel to one another, or digital lines underneath
the ADC package.
11
…111
11
…110
11
…101
00
…011
00
…010
00
…001
00
…000
01
2
FS
OUTPUT CODE
FS - 3/2LSB
INPUT VOLTAGE (LSBs)
FS = VREF
1LSB =
VREF
4096
FULL-SCALE
TRANSITION
3
Figure 10. Unipolar Transfer Function, Full Scale (FS) = VREF,
Zero Scale (ZS) = GND
CS
SCLK
DOUT
I/O
SCK
MISO
+3V TO +5V
SS
a) SPI
CS
SCLK
DOUT
CS
SCK
MISO
+3V TO +5V
SS
b) QSPI
MAX1284
MAX1285
MAX1284
MAX1285
MAX1284
MAX1285
CS
SCLK
DOUT
I/O
SK
SI
c) MICROWIRE
Figure 11. Common Serial-Interface Connections to the
MAX1284/MAX1285
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