參數(shù)資料
型號: MAX1284BESA+T
廠商: Maxim Integrated Products
文件頁數(shù): 14/15頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 400KSPS 8-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 12
采樣率(每秒): 400k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 2.5mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)單端,單極
Detailed Description
Converter Operation
The MAX1284/MAX1285 use an input T/H and succes-
sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. Figure
3 shows the MAX1284/MAX1285 in its simplest configu-
ration. The internal reference is trimmed to +2.5V. The
serial interface requires only three digital lines (SCLK,
CS, and DOUT) and provides an easy interface to
microprocessors (Ps).
The MAX1284/MAX1285 have two modes: normal and
shutdown. Pulling SHDN low shuts the device down and
reduces supply current to below 2A (typ), while pulling
SHDN high puts the device into operational mode. Pulling
CS low initiates a conversion that is driven by SCLK. The
conversion result is available at DOUT in unipolar serial
format. The serial data stream consists of three zeros,
followed by the data bits (MSB first). All transitions on
DOUT occur 20ns after the rising edge of SCLK. Figures
8 and 9 show the interface timing information.
Analog Input
Figure 4 illustrates the sampling architecture of the
ADC’s comparator. The full-scale input voltage is set by
the internal reference (VREF = +2.5V).
Track/Hold
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input (AIN) charges
capacitor CHOLD. Bringing CS low, ends the acquisition
interval. At this instant, the T/H switches the input side
of CHOLD to GND. The retained charge on CHOLD rep-
resents a sample of the input, unbalancing node ZERO
at the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0 within the limits of 12-
bit resolution. This action is equivalent to transferring a
charge from CHOLD to the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal. At the conversion’s end, the input
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
8
_______________________________________________________________________________________
DOUT
6k
Ω
DGND
CLOAD = 20pF
6k
Ω
DGND
VDD
b) High-Z to VOL and VOH to VOL
a) High-Z to VOH and VOL to VOH
Figure 1. Load Circuits for DOUT Enable Time
DOUT
6k
Ω
DGND
CLOAD = 20pF
6k
Ω
DGND
VDD
b) VOL to High-Z
a) VOH to High-Z
Figure 2. Load Circuits for DOUT Disable Time
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