MAX1284/MAX1285
side of CHOLD switches back to AIN, and CHOLD
charges to the input signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(tACQ) is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. Acquisition time is calculated by:
tACQ = 9(RS + RIN) x 12pF,
where RIN = 800
Ω, RS = the input signal’s source
impedance, and tACQ is never less than 468ns
(MAX1284) or 625ns (MAX1285). Source impedances
below 2k
Ω do not significantly affect the ADCs AC per-
formance.
Higher source impedances can be used if a 0.01F
capacitor is connected to the analog input. Note that
the input capacitor forms an RC filter with the input
source impedance, limiting the ADCs input signal
bandwidth.
Input Bandwidth
The ADCs’ input tracking circuitry has a 6MHz
(MAX1284) or 3MHz (MAX1285) small-signal band-
width, so it is possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate, by using under-
sampling techniques. To avoid aliasing of unwanted
high-frequency signals into the frequency band of inter-
est, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to VDD and GND, allow the input to swing from
(GND - 0.3V) to (VDD + 0.3V) without damage.
If the analog input exceeds 50mV beyond the sup-
plies, limit the input current to 2mA.
Internal Reference
The MAX1284/MAX1285 have an on-chip voltage refer-
ence trimmed to 2.5V. The internal reference output is
connected to REF and also drives the internal capaci-
tive DAC. The output can be used as a reference volt-
age source for other components and can source up to
800A. Bypass REF with a 4.7F capacitor. Larger
capacitors increase wake-up time when exiting shut-
down (see the
Using SHDN to Reduce Supply Current
section). The internal reference is disabled in shutdown
(SHDN = 0).
Serial Interface
Initialization after Power-Up and
Starting a Conversion
When power is first applied, and if SHDN is not pulled
low, it takes the fully discharged 4.7F reference
bypass capacitor up to 2ms to provide adequate
charge for specified accuracy. No conversions should
be performed during this time.
CHOLD
12pF
RIN
800
Ω
HOLD
CSWITCH*
6pF
*INCLUDES ALL INPUT PARASITICS
AIN
REF
GND
ZERO
AUTOZERO
RAIL
COMPARATOR
CAPACITIVE DAC
TRACK
SHUTDOWN
INPUT
ANALOG INPUT
0 TO VREF
+5V OR +3V
1
2
3
4
VDD
AIN
SHDN
REF
8
7
6
5
SCLK
CS
DOUT
GND
SERIAL
INTERFACE
4.7
μF
10
μF
0.1
μF
MAX1284
MAX1285
Figure 3. Typical Operating Circuit
Figure 4. Equivalent Input Circuit
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
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