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參數(shù)資料
| 型號： | MAX127-MAX128 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface |
| 中文描述： | 多量程，5V的，12位DAS的2線串行接口 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 124K |
| 代理商： | MAX127-MAX128 |
M
Multirange, +5V, 12-Bit DAS with
2-Wire S erial Interfac e
6
_______________________________________________________________________________________
TIMING CHARACTERISTICS (continued)
(V
DD
= +4.75V to +5.25V; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7μF at REF pin; T
A
= T
MIN
to T
MAX;
unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETERS
SYMBOL
CONDITIONS
2-WIRE STANDARD MODE
Note 1:
Accuracy specifications tested at V
DD
= 5.0V. Performance at power-supply tolerance limits is guaranteed by Power-
Supply Rejection test.
External reference: V
REF
= 4.096V, offset error nulled, ideal last-code transition = FS - 3/2LSB.
Ground “on” channel, sine wave applied to all “off” channels.
Guaranteed by design. Not tested.
Use static external load during conversion for specified accuracy.
Tested using internal reference.
PSRR measured at full scale. Tested for the ±10V (MAX127) and ±4.096V (MAX128) input ranges.
Not subject to production testing. Provided for design guidance only.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
MIN TYP MAX
UNITS
Low Period of the SCL Clock
High Period of the SCL Clock
t
LOW
t
HIGH
4.7
4.0
μs
μs
Setup Time for a Repeated
START Condition
t
SU, STA
4.7
μs
Data Hold Time
Data Setup Time
t
HD, DAT
t
SU, DAT
0
0.9
μs
ns
250
Rise Time for Both SDA and SCL
Signals (Receiving)
t
R
1000
ns
Fall Time for Both SDA and SCL
Signals (Receiving)
t
F
300
ns
Fall Time for Both SDA and SCL
Signals (Transmitting)
t
F
C
b
= total capacitance of one bus line in pF,
up to 6mA sink
20 +
0.1 x C
b
4.0
250
ns
Setup Time for STOP Condition
t
SU, STO
μs
Capacitive Load for Each
Bus Line
C
b
400
pF
Pulse Width of Spike Suppressed
t
SP
0
50
ns
Hold Time (Repeated) START
Condition
t
HD,STA
4.0
μs
Bus Free Time Between a STOP
and START Condition
t
BUF
4.7
μs
SCL Clock Frequency
f
SCL
100
kHz
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