參數(shù)資料
型號: MAX1267BEEG+T
廠商: Maxim Integrated Products
文件頁數(shù): 5/19頁
文件大小: 0K
描述: IC ADC 12BIT 265KSPS 24-QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 12
采樣率(每秒): 265k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 10mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-QSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,單極;2 個單端,雙極;1 個偽差分,單極;1 個偽差分,雙極
MAX1265/MAX1267
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
______________________________________________________________________________________
13
External Clock Mode
To select the external clock mode, bits D6 and D7 of
the control byte must be set to 1. Figure 6 shows the
clock and WR timing relationship for internal (Figure 6a)
and external (Figure 6b) acquisition modes with an
external clock. For proper operation, a 100kHz to
4.8MHz clock frequency with 30% to 70% duty cycle is
recommended. Operating the MAX1265/MAX1267 with
clock frequencies lower than 100kHz is not recommend-
ed, because the resulting voltage droop across the hold
capacitor in the T/H stage degrades performance.
Digital Interface
The input and output data are multiplexed on a tri-state
parallel interface (I/O) that can easily be interfaced with
standard Ps. The signals CS, WR, and RD control the
write and read operations. CS represents the chip-
Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
Figure 6b. External Clock and WR Timing (External Acquisition Mode)
WR
CLK
WR
WR GOES HIGH WHEN CLK IS HIGH.
WR GOES HIGH WHEN CLK IS LOW.
tCWS
tCH
tCL
tCP
tCWH
ACQUISITION STARTS
CONVERSION STARTS
ACQUISITION ENDS
ACQMOD = 0
WR
CLK
WR
WR GOES HIGH WHEN CLK IS HIGH
WR GOES HIGH WHEN CLK IS LOW
tDH
tCWH
tCWS
ACQUISITION STARTS
CONVERSION STARTS
ACQUISITION ENDS
ACQMOD = 1
ACQMOD = 0
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