參數(shù)資料
型號(hào): MAX1247BMJE
廠(chǎng)商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): ADC
英文描述: +2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16
中文描述: 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP16
封裝: CERDIP-16
文件頁(yè)數(shù): 13/24頁(yè)
文件大?。?/td> 223K
代理商: MAX1247BMJE
M
+2.7V, Low-Power, 4-Channel,
S erial 12-Bit ADCs in QS OP-16
______________________________________________________________________________________
13
conversion already in progress. When internal clock
mode is selected, SSTRB does not go into a high-
impedance state when
CS
goes high.
Figure 9 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1246/MAX1247 at clock rates exceeding
2.0MHz if the minimum acquisition time (t
ACQ
) is kept
above 1.5μs.
Data Framing
The falling edge of
CS
does
not
start a conversion.
The first logic high clocked into DIN is interpreted as a
start bit and defines the first bit of the control byte. A
conversion starts on SCLK’s falling edge, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as follows:
The first high bit clocked into DIN with
CS
low any
time the converter is idle; e.g., after V
DD
is applied.
OR
The first high bit clocked into DIN after bit 5 of a con-
version in progress is clocked onto the DOUT pin.
If CS is toggled before the current conversion is com-
plete, the next high bit clocked into DIN is recognized as
a start bit; the current conversion is terminated, and a
new one is started.
SSTRB
CS
SCLK
DIN
DOUT
1
4
8
12
18
20
24
START
SEL2 SEL1 SEL0
UNI/
BIP
SGL/
DIF
PD1
PD0
B11
B10
B9
B2
B1
B0
FILLED WITH
ZEROS
IDLE
CONVERSION
7.5
μ
s MAX
(SHDN = FLOAT)
2
3
5
6
7
9
10
11
19
21
22
23
t
CONV
ACQUISITION
1.5
μ
s
(f
SCLK
= 2MHz)
IDLE
A/D STATE
Figure 8. Internal Clock Mode Timing
t
SDV
t
SSTRB
PD0 CLOCKED IN
t
STR
SSTRB
SCLK
CS
t
SSTRB
Figure 7. External Clock Mode SSTRB Detailed Timing
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