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參數(shù)資料
| 型號： | MAX1240BESA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SERIAL 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 73k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 471mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
VDD = 3.6V
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V (MAX1240); VDD = +2.7V to +5.25V (MAX1241); 73ksps, fSCLK = 2.1MHz (50% duty cycle); MAX1240—4.7F
capacitor at REF pin, MAX1241—external reference; VREF = 2.500V applied to REF pin; TA = TMIN to TMAX; unless otherwise noted.)
Note 1: Tested at VDD = +2.7V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3: MAX1240—internal reference, offset nulled; MAX1241—external reference (VREF = +2.500V), offset nulled.
Note 4: External load should not change during conversion for specified accuracy.
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: Measured as [VFS(2.7V) - VFS(VDD(MAX)].
Note 7: To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum
time needed for the signal to be acquired.
SCLK Pulse Width Low
tCL
200
ns
SCLK Pulse Width High
tCH
200
ns
SCLK Clock Frequency
fSCLK
0
2.1
MHz
CS Rise to Output Disable
tTR
240
ns
SCLK Low to CS Fall Setup Time
tCS0
50
ns
DOUT Rise to SCLK Rise (Note 5)
tSTR
0
ns
CS Pulse Width
tCS
240
ns
Figure 2, CLOAD = 50pF
CS Fall to Output Enable
tDV
240
ns
Figure 1, CLOAD = 50pF
PARAMETERS
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
Acquisition Time
tACQ
1.5
s
CS = VDD (Note 6)
TIMING CHARACTERISTICS (Figure 8)
(VDD = +2.7V to +3.6V (MAX1240); VDD = +2.7V to +5.25V (MAX1241); TA = TMIN to TMAX, unless otherwise noted.)
PARAMETERS
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
2.7
3.6
MAX1240
2.7
5.25
MAX1241
VDD
Supply Voltage
V
±0.3
(Note 5)
PSR
Supply Rejection
mV
20
240
SCLK Fall to Output Data Valid
tDO
20
200
ns
Figure 1,
CLOAD = 50pF
MAX124_ _C/E
MAX124_ _M
1.4
2.0
Operating
mode
1.6
2.5
VDD = 3.6V
3.5
15
VDD = 5.25V
VDD = 3.6V
VDD = 5.25V
IDD
1.9
10
Power-down, digital inputs
at 0V or VDD
1.4
3.5
A
0.9
1.5
VDD = 3.6V
MAX1240C
MAX1241A/B
Supply Current
MAX1240A/B
mA
1.6
3.8
VDD = 3.6V
VDD = 5.25V
0.9
2.8
MAX1241C
POWER REQUIREMENTS
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