參數(shù)資料
型號(hào): MAX1231EVKIT
廠商: Maxim Integrated Products
文件頁數(shù): 21/22頁
文件大小: 0K
描述: EVAL KIT FOR MAX1231
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 12
采樣率(每秒): 300k
數(shù)據(jù)接口: 串行
輸入范圍: ±VREF/2
在以下條件下的電源(標(biāo)準(zhǔn)): 1.86mW @ 300kSPS
工作溫度: 0°C ~ 70°C
已用 IC / 零件: MAX1231
已供物品: 板,CD
MAX1227/MAX1229/MAX1231
12-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
8
_______________________________________________________________________________________
Pin Description
PIN
MAX1231
TQFN-EP
MAX1231
QSOP
MAX1229
MAX1227
NAME
FUNCTION
2–12, 26,
27, 28,
1–14
AIN0–13
Analog Inputs
1–10
AIN0–9
Analog Inputs
1–6
AIN0–5
Analog Inputs
13
15
REF-/AIN14
Negative Input for External Differential Reference/Analog Input 14.
See Table 3 for details on programming the setup register.
11
REF-/AIN10
Negative Input for External Differential Reference/Analog Input 10.
See Table 3 for details on programming the setup register.
7
REF-/AIN6
Negative Input for External Differential Reference/Analog Input 6.
See Table 3 for details on programming the setup register.
14
16
CNVST/
AIN15
Active-Low Conversion Start Input/Analog Input 15. See Table 3 for
details on programming the setup register.
12
CNVST/
AIN11
Active-Low Conversion Start Input/Analog Input 11. See Table 3 for
details on programming the setup register.
———
8
CNVST/
AIN7
Active-Low Conversion Start Input/Analog Input 7. See Table 3 for
details on programming the setup register.
15
17
13
9
REF+
Positive Reference Input. Bypass to GND with a 0.1F capacitor.
16
18
14
10
GND
Ground
18
19
15
11
VDD
Power Input. Bypass to GND with a 0.1F capacitor.
20
16
12
SCLK
Serial Clock Input. Clocks data in and out of the serial interface.
(Duty cycle must be 40% to 60%.) See Table 3 for details on
programming the clock mode.
21
17
13
CS
Active-Low Chip Select Input. When CS is low, the serial interface
is enabled. When CS is high, DOUT is high impedance.
22
18
14
DIN
Serial Data Input. DIN data is latched into the serial interface on the
rising edge of SCLK.
23
19
15
DOUT
Serial Data Output. Data is clocked out on the falling edge of
SCLK. High impedance when CS is connected to VDD.
24
20
16
EOC
End of Conversion Output. Data is valid after EOC pulls low.
1, 17, 19,
25
N.C.
No Connection. Not internally connected.
EP
Exposed Pad (TQFN Only). Connect to GND.
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