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參數(shù)資料
| 型號(hào)： | MAX1203ACAP |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 5v, 8-cHANNEL, sERIAL, 12-bIT adcS WITH 3v dIGITAL iNTERFACE |
| 中文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | 5.30 MM, 0.65 MM PITCH, PLASTIC, SSOP-20 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 309K |
| 代理商： | MAX1203ACAP |
M
5V, 8-Channel, S erial, 12-Bit ADCs
with 3V Digital Interfac e
______________________________________________________________________________________
15
Figure 9. Internal Clock Mode Timing
SSTRB
CS
SCLK
DIN
DOUT
1
4
8
12
18
20
24
START
SEL2 SEL1 SEL0
BIP
DIF
PD1
PD0
B11
B10
B9
B2
B1
B0
ACQUISITION
1.5μs
(SCLK = 2MHz)
IDLE
FILLED WITH
ZEROS
IDLE
CONVERSION
10μs MAX
ADC STATE
2
3
5
6
7
9
10
11
19
21
22
23
t
CONV
Figure 10. Internal Clock Mode SSTRB Detailed Timing
PD0 CLOCK IN
t
SSTRB
t
CSH
t
CONV
t
SCK
SSTRB
SCLK
t
CSS
NOTE: KEEP SCLK LOW DURING CONVERSION FOR BEST NOISE PERFORMANCE.
CS
conversion is started. Pulling
CS
high prevents data from
being clocked into the MAX1202/MAX1203 and three-
states DOUT, but it does not adversely affect an internal
clock mode conversion already in progress. When
internal clock mode is selected, SSTRB does not go into
a high-impedance state when
CS
goes high.
Figure 10 shows SSTRB timing in internal clock mode.
Data can be shifted in and out of the MAX1202/MAX1203
at clock rates up to 2.0MHz, if t
ACQ
is kept above 1.5μs.
Data Framing
CS
’s falling edge does
not
start a conversion on the
MAX1202/MAX1203. The first logic high clocked into DIN
is interpreted as a start bit and defines the first bit of the
control byte. A conversion starts on SCLK’s falling edge
after the eighth bit of the control byte (the PD0 bit) is
clocked into DIN. The start bit is defined as one of the
following:
The first high bit clocked into DIN with
CS
low any-
time the converter is idle (e.g., after V
DD
is applied).
or
The first high bit clocked into DIN after bit 5 (B5) of a
conversion in progress appears at DOUT.
If a falling edge on
CS
forces a start bit before B5
becomes available, the current conversion is termi-
nated and a new one started. Thus, the fastest the
MAX1202/MAX1203 can run is 15 clocks/conversion.
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| MAX1203ACAP+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 8Ch 133ksps 5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1203ACAP+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 8Ch 133ksps 5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1203ACAP-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1203ACPP | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1203ACPP+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 8Ch 133ksps 5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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