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| 型號(hào)： | MAX1202BMJP |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 5v, 8-cHANNEL, sERIAL, 12-bIT adcS WITH 3v dIGITAL iNTERFACE |
| 中文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 309K |
| 代理商： | MAX1202BMJP |
M
5V, 8-Channel, S erial, 12-Bit ADCs
with 3V Digital Interfac e
6
_______________________________________________________________________________________
TIMING CHARACTERISTICS
(V
DD
= +5V ±5%, VL = 2.7V to 3.6V, V
SS
= 0V or -5V ±5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Tested at V
DD
= 5.0V; V
SS
= 0V; unipolar-input mode.
Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
MAX1202—internal reference, offset nulled; MAX1203—external reference (V
REF
= 4.096V), offset nulled.
On-channel grounded; sine wave applied to all off-channels.
Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Guaranteed by design. Not subject to production testing.
Common-mode range for analog inputs is from V
SS
to V
DD
.
External load should not change during the conversion for specified accuracy.
Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND;
REFADJ = GND. Shutdown supply current is also dependent on V
IH
(Figure 12c).
Note 10:
Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (
CS
high). When the outputs are
active (
CS
low), the logic supply current depends on f
SCLK
, and on the static and capacitive load at DOUT and SSTRB.
Note 11:
Measured at V
SUPPLY
+ 5% and V
SUPPLY
- 5% only.
Note 12:
Measured at VL = 2.7V and VL = 3.6V.
ns
ns
ns
ns
ns
100
0
200
200
t
CSS
t
CSH
t
CH
t
CL
t
SSTRB
External-clock mode only, C
LOAD
= 100pF
ns
CS
to SCLK Rise Setup
CS
to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
240
C
LOAD
= 100pF
C
LOAD
= 100pF
ns
ns
ns
20
240
240
240
t
DO
t
DV
t
TR
SCLK Fall to Output Data Valid
CS
Fall to Output Enable
CS
Rise to Output Disable
CONDITIONS
t
SDV
CS
Fall to SSTRB Output Enable
(Note 6)
External-clock mode only, C
LOAD
= 100pF
ns
240
t
STR
CS
Rise to SSTRB Output
Disable (Note 6)
Internal-clock mode only
ns
0
t
SCK
SSTRB Rise to SCLK Rise
(Note 6)
C
LOAD
= 100pF
240
C
LOAD
= 100pF
ns
0
t
DH
DIN to SCLK Hold
μs
ns
1.5
100
t
ACQ
t
DS
Acquisition Time
DIN to SCLK Setup
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
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