參數(shù)資料
型號: MAX1202BEAP+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/24頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 8CH 20-SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 12
采樣率(每秒): 133k
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 640mW
電壓電源: 雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 20-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個單端,單極;8 個單端,雙極;4 個差分,單極;4 個差分,雙極
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
10
______________________________________________________________________________________
Track/Hold
The T/H enters tracking mode on the falling clock edge
after the fifth bit of the 8-bit control word is shifted in. The
T/H enters hold mode on the falling clock edge after the
eighth bit of the control word is shifted in. IN- is con-
nected to GND if the converter is set up for single-ended
inputs, and the converter samples the “+” input. IN- con-
nects to the “-” input if the converter is set up for differen-
tial inputs, and the difference of
|N+ - IN- is sampled.
The positive input connects back to IN+, at the end of
the conversion, and CHOLD charges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
acquisition time increases and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following:
tACQ = 9 x (RS + RIN) x 16pF
where RIN = 9k, RS = the source impedance of the
input signal, and tACQ is never less than 1.5s. Source
impedances below 1k
do not significantly affect the
ADC’s AC performance. Higher source impedances can
be used if an input capacitor is connected to the analog
inputs, as shown in Figure 5. Note that the input capaci-
tor forms an RC filter with the input source impedance,
limiting the ADC’s signal bandwidth.
Figure 5. Quick-Look Circuit
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
GND
CSWITCH
TRACK
T/H
SWITCH
9k
RIN
CHOLD
HOLD
12-BIT CAPACITIVE DAC
REF
ZERO
COMPARATOR
+
16pF
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = GND.
DIFFERENTIAL MODE:
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
0.1F
4.7F
VDD
GND
VSS
CS
SCLK
DIN
DOUT
SSTRB
SHDN
+3V
N.C.
0.01F
CH7
VL
REFADJ
+2.5V
REFERENCE
REF
C2
0.01F
C1
4.7F
+2.5V
**
0V TO
4.096V
ANALOG
INPUT
0.1F
+3V
OSCILLOSCOPE
CH1
CH2
CH3
CH4
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX).
**REQUIRED FOR MAX1203 ONLY.
MAX1202
MAX1203
+5V
2MHz
OSCILLATOR
SCLK
SSTRB
DOUT*
Figure 4. Equivalent Input Circuit
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