參數(shù)資料
型號： MAX1200BCMH
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： ADC
英文描述： +5v sINGLE-sUPPLY, 1mSPS, 16-bIT sELF-cALIBRATING adc
中文描述： 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44
封裝： M0-108AA-2, MQFP-44
文件頁數(shù)： 4/16頁
文件大?。?/td> 204K
代理商： MAX1200BCMH
M
+5V S ingle-S upply, 1Msps, 16-Bit
S elf-Calibrating ADC
4
_______________________________________________________________________________________
DIGITAL INPUT AND OUTPUT CHARACTERISTICS
(AV
DD
= +5V ±5%, DV
DD
= DRV
DD
= +3.3V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
Note 1:
Reference inputs driven by operational amplifiers for Kelvin-sensed operation.
Note 2:
For unipolar mode, the analog input voltage, V
INP
, must be within 0 and V
REF
, V
INN
= V
CM
/ 2; where V
REF
= V
RFPS
- V
RFNS
.
For differential mode, the analog input voltages V
INP
and V
INN
must be within 0 and V
REF
; where V
REF
= V
RFPS
- V
RFNS
. The
common-mode voltage of the inputs INP and INN is V
CM=
(V
RFPS +
V
RFNS
) / 2.
Note 3:
R
I
varies inversely with sample rate.
Note 4:
Minimum and maximum parameters are not tested. Guaranteed by design.
Note 5:
Calibration remains valid for temperature changes within ±20°C and power-supply variations ±5%. Guaranteed by design.
Note 6:
All AC specifications are shown for the differential mode.
I
SOURCE
= 200μA
V
IN
= 0 or DV
DD
I
SINK
= 1.6mA
CONDITIONS
4
Input Capacitance
CLK Input LOW Voltage
CLK Input HIGH Voltage
CLK Input Current
DV
DD
- 0.8
V
IH
0.8
V
IL
Input LOW Voltage
Input HIGH Voltage
DV
DD
- 0.4
DV
DD
- 0.03
V
OH
Output High Voltage
0.8
V
CLK
V
CLK
I
CLK
AV
DD
- 0.8
9
C
CLK
I
IN
V
OL
CLK Input Capacitance
Digital Input Current
Output Low Voltage
±0.1
70
±10
400
MIN
TYP
MAX
SYMBOL
PARAMETER
±0.1
3.5
±10
I
LEAKAGE
C
OUT
Three-State Leakage Current
Three-State Output Capacitance
mV
μA
pF
pF
V
V
μA
V
V
V
pF
μA
UNITS
V
IN
= 0 or V
DD
±1
±10
C
L
= 20pF
CONDITIONS
ns
ns
ns
187
187
244
244
t
CLK
/ 2
301
301
t
CH
t
CL
t
ACQ
Clock HIGH Time
Clock LOW Time
Acquisition Time
ns
488
t
CLK
ns
4 / f
SAMPLE
t
CONV
Conversion Time
Clock Period
ns
f
CLK
Cycles
16
75
t
REL
Bus Relinquish Time
ns
16
75
t
AC
Data Access Time
ns
ns
ns
70
150
t
OD
t
DAV
t
S
Output Delay
DAV Pulse Width
CLK-to-DAV Rising Edge
1 / f
CLK
65
145
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ST_CAL = DV
DD
17,400
t
CAL
Calibration Time
TIMING CHARACTERISTICS (Figures 7, 8, 9)
(AV
DD
= +5V ±5%, DV
DD
= DRV
DD
= +3.3V, f
CLK
= 2.048MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
T
A
= +25°C.) (Note 1)
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