參數(shù)資料
型號(hào)： MAX1185
廠商： Maxim Integrated Products, Inc.
英文描述： Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
中文描述： 雙路、10位、20Msps、+3V、低功耗ADC，內(nèi)置電壓基準(zhǔn)及復(fù)用并行輸出
文件頁(yè)數(shù)： 13/20頁(yè)
文件大?。?/td> 495K
代理商： MAX1185
M
Dual 10-Bit, 20Msps, +3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
______________________________________________________________________________________
13
Applications Information
Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a V
DD
/2 output voltage for level
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat-
ed with high-speed operational amplifiers that follows
the amplifiers. The user may select the R
ISO
and C
IN
values to optimize the filter performance, to suit a par-
ticular application. For the application in Figure 5, a
R
ISO
of 50
is placed before the capacitive load to
prevent ringing and oscillation. The 22pF C
IN
capacitor
acts as a small bypassing capacitor.
Using Transformer Coupling
An RF transformer (Figure 6) provides an excellent
solution to convert a single-ended source signal to a
fully differential signal, required by the MAX1185 for
optimum performance. Connecting the center tap of the
transformer to COM provides a V
DD
/2 DC level shift to
the input. Although a 1:1 transformer is shown, a step-
up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the over-
all distortion.
In general, the MAX1185 provides better SFDR and
THD with fully differential input signals than single-
ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires
half the signal swing compared to single-ended mode.
t
DOB
t
CL
t
CH
t
CLK
t
DOA
t
DA/B
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
A/B
CHB
D0A/B-D9A/B
D0B
CHA
D1A
CHB
D1B
CHA
D2A
CHB
D2B
CHA
D3A
CHB
D3B
CHA
D4A
CHB
D4B
CHA
D5A
CHB
D5B
CHA
D6A
CHB
D6B
CHA
CHB
CLK
OUTPUT
D0A/B
–
D9A/B
OE
t
DISABLE
t
ENABLE
HIGH-Z
HIGH-Z
VALID DATA
Figure 3. Timing Diagram for Multiplexed Outputs
Figure 4. Output Timing Diagram
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