參數(shù)資料
型號(hào): MAX1184ECM+D
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 3/21頁(yè)
文件大?。?/td> 0K
描述: IC ADC 10BIT 20MSPS DUAL 48-TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 250
位數(shù): 10
采樣率(每秒): 20M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 150mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-TQFP 裸露焊盤(7x7)
包裝: 托盤
輸入數(shù)目和類型: 4 個(gè)單端,雙極;2 個(gè)差分,雙極
產(chǎn)品目錄頁(yè)面: 1396 (CN2011-ZH PDF)
Detailed Description
The MAX1184 uses a 9-stage, fully-differential
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
Counting the delay through the output latch, the clock-
cycle latency is five clock cycles.
1.5-bit (2-comparator) flash ADCs convert the held-
input voltages into a digital code. The digital-to-analog
converters (DACs) convert the digitized results back
into analog voltages, which are then subtracted from
the original held input signals. The resulting error sig-
nals are then multiplied by two and the residues are
passed along to the next pipeline stages, where the
process is repeated until the signals have been
processed by all nine stages. Digital error correction
compensates for ADC comparator offsets in each of
these pipeline stages and ensures no missing codes.
MAX1184
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
______________________________________________________________________________________
11
VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE-ENDED)
VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE-ENDED)
T/H
VOUT
x2
Σ
FLASH
ADC
DAC
1.5 BITS
10
VINB
VIN
STAGE 1
STAGE 2
D9B–D0B
DIGITAL CORRECTION LOGIC
STAGE 8
STAGE 9
2-BIT FLASH
ADC
T/H
VOUT
x2
Σ
FLASH
ADC
DAC
1.5 BITS
10
VINB
STAGE 1
STAGE 2
D9B–D0B
DIGITAL CORRECTION LOGIC
STAGE 8
STAGE 9
2-BIT FLASH
ADC
T/H
Figure 1. Pipelined Architecture—Stage Blocks
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