參數(shù)資料
型號: MAX1180ECM
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC with Internal Reference and Parallel Outputs
中文描述: 2-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP48
封裝: 7 X 7 MM, 1 MM HEIGHT, MS-026ABA-HD, TQFP-48
文件頁數(shù): 13/20頁
文件大?。?/td> 573K
代理商: MAX1180ECM
M
Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
______________________________________________________________________________________
13
requires a reduced full-scale range. For stability and
noise filtering purposes, bypass REFIN with a >10nF
capacitor to GND. In internal reference mode, REFOUT,
COM, REFP, and REFN become low-impedance out-
puts.
In the buffered external reference mode, adjust the ref-
erence voltage levels externally by applying a stable
and accurate voltage at REFIN. In this mode, COM,
REFP, and REFN become outputs. REFOUT may be left
open or connected to REFIN through a >10k
resistor.
In the unbuffered external reference mode, connect
REFIN to GND. This deactivates the on-chip reference
buffers for REFP, COM, and REFN. With their buffers
shut down, these nodes become high impedance and
may be driven through separate external reference
sources.
Clock Input (CLK)
The MAX1180
s CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (< 2ns). In particular,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR perfor-
mance of the on-chip ADCs as follows:
DIFFERENTIAL INPUT
VOLTAGE*
DIFFERENTIAL INPUT
STRAIGHT OFFSET
BINARY
T/B = 0
TWO
S COMPLEMENT
T/B = 1
V
REF
511/512
V
REF
1/512
0
-V
REF
1/512
-V
REF
511/512
-V
REF
512/512
+FULL SCALE - 1LSB
+ 1 LSB
Bipolar Zero
- 1 LSB
-FULL SCALE + 1 LSB
-FULL SCALE
11 1111 1111
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
11 1111 1111
10 0000 0001
10 0000 0000
Table 1. MAX1180 Output Codes For Differential Inputs
N - 6
N
N - 5
N + 1
N - 4
N + 2
N - 3
N + 3
N - 2
N + 4
N - 1
N + 5
N
N + 6
N + 1
5 CLOCK-CYCLE LATENCY
ANALOG INPUT
CLOCK INPUT
DATA OUTPUT
D9A
D0A
t
D0
t
CH
t
CL
N - 6
N - 5
N - 4
N - 3
N - 2
N - 1
N
N + 1
DATA OUTPUT
D9B
D0B
Figure 3. System Timing Diagram
*V
REF
= V
REFP
– V
REFN
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