參數(shù)資料
型號: MAX11802ETC+T
廠商: Maxim Integrated Products
文件頁數(shù): 38/59頁
文件大?。?/td> 0K
描述: IC TOUCH SCREEN CTLR 12-TQFN
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
類型: 電阻
觸摸面板接口: 4 線
輸入數(shù)/鍵: 1 TSC
分辨率(位): 12 b
數(shù)據接口: 串行,SPI?
數(shù)據速率/采樣率 (SPS,BPS): 105k
電源電壓: 1.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 12-WQFN 裸露焊盤
供應商設備封裝: 12-TQFN-EP(4x4)
包裝: 帶卷 (TR)
Read Data Format
Send the slave address with the R/W bit set to 1 to initi-
ate a read operation. The MAX11801/MAX11803
acknowledge receipt of its slave address by pulling
SDA low during the 9th SCL clock pulse. Transmitted
data is valid on the rising edge of SCL. A STOP condi-
tion can be issued after any number of read data bytes.
The address pointer should be preset to a specific reg-
ister before a read command is issued. The master pre-
sets the address pointer by first sending the
MAX11801/MAX11803’s slave address with the R/W bit
set to 0 followed by the selected register address. A
repeated START condition is then sent followed by the
slave address with the R/W bit set to 1. The MAX11801/
MAX11803 then transmit the contents of the selected
register. If the selected register supports autoincrement,
the register pointer automatically increments after trans-
mitting each data byte, making data in the next register
location available for access in the same transfer. Some
registers do not support autoincrement, usually
because they are at the end of a functional section or,
in the case of the FIFO, store multiple records.
The master acknowledges receipt of each data byte
received from the MAX11801/MAX11803 during the
“acknowledge clock period.” If the master requires
more data from the MAX11801/MAX11803, it brings the
acknowledge line low, indicating more data is expect-
ed. This sequence is repeated until the master termi-
nates with a not-acknowledge (~A) followed by a STOP
condition. Figure 27 illustrates the frame format for
MAX11800–MAX11803
Low-Power, Ultra-Small Resistive Touch-Screen
Controllers with I2C/SPI Interface
______________________________________________________________________________________
43
START
WRITE ADDRESS
BYTE 1: DEVICE ADDRESS
WRITE REGISTER START NUMBER
BYTE 2: FIRST REG NUMBER = N
STOP
W
N3 N2 N1 N0
X
D
READ DATA
BYTE 4: REG(N)[7:0] DATA
REPEATED
START
ADDITONAL
SEQUENTIAL READ
DATA BYTES
READ DATA
D
D~A
D
READ DATA (LAST BYTE)
R
WRITE ADDRESS
BYTE 3: DEVICE ADDRESS
ACKNOWLEDGE GENERATED BY I2C MASTER
ACKNOWLEDGE GENERATED BY MAX11801/MAX11803
N4
N5
N6
1
0
1
0
A1 A0
1
0
1
0 A1 A0
SDA
SCL
AA
A
A = ACKNOWLEDGE
~A = NOT ACKNOWLEDGE
Figure 28. I2C Multiple Read Sequence
SDA
DIRECTION
SCL
1
0
1
0
A1
A0
W
N6
N5
N4
N3
N2
N1
N0
X
ACK
OUT
IN
OUT
INTO MAX11801/MAX11803
SDA (cont.)
SCL (cont.)
0
A1
D7
D6
D5
D4
D3
D2
D1
D0
ACK
OUT
A0
IN
START
1
0
1
R
Sr
STOP
NACK
START
WRITE ADDRESS
BYTE 1: DEVICE ADDRESS
WRITE REGISTER START NUMBER
BYTE 2: FIRST REG NUMBER = N
STOP
READ DATA
BYTE 4: REG(N)[7:0] DATA
REPEATED
START
WRITE ADDRESS
BYTE 3: DEVICE ADDRESS
ACKNOWLEDGE GENERATED BY I2C MASTER
ACKNOWLEDGE GENERATED BY MAX11801/MAX11803
A = ACKNOWLEDGE
~A = NOT ACKNOWLEDGE
1
SDA
SCL
0
1
0
A1
N6 N5 N4 N3 N2 N1 N0
1
0
1
0
A1
AD
D
~A
R
A2
X
A
A2
A
W
Figure 27. Basic Single Read Sequence
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