MAX11800–MAX11803
Low-Power, Ultra-Small Resistive Touch-Screen
Controllers with I2C/SPI Interface
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41
on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA while SCL is high (Figure 23). A
START condition from the master signals the beginning
of a transmission to the MAX11801/MAX11803. The
master terminates transmission and frees the bus by
issuing a STOP condition. The bus remains active if a
repeated START condition is generated instead of a
STOP condition.
Early STOP Conditions
The MAX11801/MAX11803 recognize a STOP condition
at any point during data transmission, except if the
STOP condition occurs in the same high pulse as a
START condition. For proper operation, do not send a
STOP condition during the same SCL high pulse as the
START condition.
Slave Address
The slave address is defined as the seven most signifi-
cant bits (MSBs) followed by the read/write bit (R/W). For
the MAX11801/MAX11803 the seven most significant bits
are 10010 A1 A0, where A1 and A0 are user config-
urable through the address input pins A1 and A0. The
LSB is the read/write bit. Setting the R/W bit to 1 config-
ures the MAX11801/MAX11803 for read mode. Setting
the R/W bit to 0 configures the MAX11801/MAX11803
for write mode. The address is the first byte of informa-
tion sent to the MAX11801/MAX11803 after the START
condition. See Figures 25 and 26 for details.
I2C Slave Address = 1 0 0 1 0 A1 A0 R/W
I2C Register Address
The register addresses are defined as the seven most
significant bits (MSBs) followed by a don’t care bit. The
format is N N N N N N N X, where N is the register
address and X is a don’t care.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX11801/MAX11803 use to handshake receipt each
byte of data when in write mode (see Figure 24). The
MAX11801/MAX11803 pull down SDA during the entire
128
9
START
CONDITION
SCL
SDA
ACKNOWLEDGE
NOT ACKNOWLEDGE
CLOCK PULSE FOR
ACKNOWLEDGEMENT
Figure 24. Acknowledge
SCL
SDA
SSr
P
Figure 23. START, STOP, and Repeated START Conditions
Figure 22. 2-Wire Interface Timing Diagram
SDA
SCL
S
tF
tHD;STA
tLOW
tR
tHD;DAT
tSU;DAT
tHIGH
tF
tSU;STA
tHD;STA
Sr
tSP
tBUF
tSU;STO
P
S